AMBA 5 is the latest generation of the freely available AMBA protocol specifications. It introduces the Coherent Hub Interface (CHI) architecture, which defines the interfaces to connect fully coherent processors and high-performance interconnects. AMBA 5 also introduces the AXI5, ACE5 and AHB5 protocols, which extend prior generations to include a number of performances and scalability features, and to align and complement CHI.
Find out more about the major revisions to the AMBA AXI and CHI specifications.
The AMBA Coherent Hub Interface (CHI) specification defines the interfaces to connect fully coherent processors. For example, the Cortex-A76 and Cortex-A65, and dynamic memory controllers, such as the CoreLink DMC-620, to high-performance, non-blocking interconnects, such as the CoreLink CMN-600. It is appropriate for a wide range of applications that require coherency, including mobile, networking, automotive, and datacenters.
The AMBA CHI specification separates the protocol and transport layers to allow differing implementations that enable the optimal trade-offs between performance, power, and area. This separation allows interconnect designs ranging from an efficient, small cross bar to high-performance, large scale mesh networks.
AMBA CHI has been architected to maintain performance, as the number of components and quantity of traffic rises. This includes placing additional requirements on requesters to respond to coherent snoop transactions, so forward progress for particular requesters can be more easily guaranteed in a congested system. The separation of the identification mechanism into requester identifiers and transaction identifiers means the interconnect can be constructed in a more efficient manner.
The protocol also provides a Quality of Service (QoS) mechanism to control how resources in the system, shared by many processors, are allocated without a detailed understanding of every component and how they might interact.
Some of the key features include:
- Support for high frequency, non-blocking coherent data transfer between many processors.
- A layered model to allow separation of communication and transport protocols for flexible topologies, such as a cross bar, ring, mesh, or ad hoc.
- Cache stashing to allow accelerators or IO devices to stash critical data within a CPU cache for low latency access.
- Far atomic operations to enable the interconnect to perform high-frequency updates to shared data.
- End-to-end data protection and poisoning signaling.
Issue D of the AMBA CHI specification introduces the AMBA interface parity extension for use in applications including automotive, with resilience or functional safety requirements. CPUs, such as the Cortex-A78AE, include this feature and are designed to undertake complex and demanding safety-critical tasks with varying workloads.
Issue E of the AMBA CHI specification adds new optional features, such as Memory Tagging (MTE), multiple interfaces, replicated channels, and a series of new transaction types and optimizations.
AMBA CHI Specification Introduction to AMBA CHI Guide Atomic Transactions in AMBA CHI
AMBA AXI and ACE
The AMBA AXI (Advanced eXtensible Interface) and ACE (AXI Coherency Extension) specification defines the protocols to implement high-frequency, high-bandwidth interconnect designs across a wide range of applications, including mobile, consumer, networking, automotive, and embedded. ACE5, ACE5-Lite, and AXI5 protocols extend prior generations to include a number of performance and scalability features which align and complement AMBA CHI.
Some of the new features and options include:
- Atomic transactions
- Cache stashing
- Data protection and poisoning signaling
- Armv8.1 Distributed Virtual Memory (DVM) messages
- Quality of Service Accept signaling
- Persistent Cache Maintenance Operations (CMO)
- Cache de-allocation transactions
Issue G of the AMBA AXI and ACE specification adds new optional features, such as:
- Interface parity protection for use in applications including automotive, with resilience or functional safety requirements. CPUs, such as the Cortex-A78AE, include this feature and are designed to undertake complex and demanding safety-critical tasks with varying workloads.
- Unique ID indicator.
- Memory Partitioning and Monitoring (MPAM).
Issue H of the specification adds further optional features. For example:
- Memory Tagging Extensions (MTE)
- Armv8.4 DVM messages
- Prefetch request and response
- Write with cache maintenance operations
- Write to zero without data transfer
The AMBA Advanced High-performance Bus (AHB) specification defines an interface protocol most widely used with Cortex-M processors, for embedded designs and other low latency SoCs. The AHB5 protocol builds upon the previous generation of AHB-Lite with two key goals:
- To complement the Armv8-M architecture and extend the TrustZone security foundation from the processor to the entire system.
- To provide consistency and alignment with the AMBA 4 AXI specification to:
- Ease integration of Cortex-A and Cortex-M based systems in a SoC.
- Allow a unified TrustZone security solution inclusive of AXI and AHB systems.
The new properties introduced in the specification are:
- Secure/Non-secure signaling in address phase to indicate secure or non-secure transactions.
- Extended memory types to support more complex systems.
- Exclusive transfers that support semaphore-type operations.
The AHB5 provides further clarifications of AHB-Lite protocol properties, as they become more widely adopted:
- Multiple subordinate select for area efficiency.
- Single-copy and multi-copy atomicity enabling scaling to multiple cores.
- User signaling allowing for user extensions and consistency with the AMBA 4 AXI specification.
Issue C of the AMBA AHB specification adds new optional features, such as the interface parity protection and write strobes.
Highly compact and low power, it allows configuration and low bandwidth traffic to be isolated from high-performance interconnects. APB supports the low-bandwidth transactions required to access configuration registers and low-bandwidth data traffic in peripherals.
Issue D of the AMBA APB specification defines the APB5 interface and introduces new features, such as the interface parity protection and wake-up signaling.
The AMBA ATB is a data-agnostic interface for transferring trace information between components in a trace system. Issue C of the specification adds wake-up signaling.
AMBA AXI-Stream defines an interface for unidirectional data transfers with greatly reduced signal routing. Key features are:
- Support for single and multiple data streams using the same set of shared wires.
- Support for multiple data widths within the same interconnect.
- Ideal for implementation in FPGA.
Issue B of the AMBA AXI-Stream specification defines the AXI5-Stream and introduces new features, such as the interface parity protection and wake-up signaling.
The AMBA CXS specification defines a credited, non-blocking streaming interface protocol, used in point-to-point packetized communications. It is optimized for the transport of CCIX and CXL packets between an on-chip interconnect and a PCIe controller. CXS is also optimized for wide interfaces, which enables passing packets to a high-data-rate external interface and merging of multiple packets into a single transfer. Issue B of the CXS specification introduces support for multiple protocol streams.
The AMBA Adaptive Traffic Profiles (AMBA ATP) is a synthetic traffic framework capable of modeling systems' transmitter and receiver high-level memory access behavior in a concise, simple, and portable way. Traffic Profiles can be used across multiple tools and design/verification environments to assist with the design and verification of complex SoCs. Among other use cases, they enable a simpler and faster simulation mechanism that is also predictable and adaptive.
The AMBA Distributed Translation Interface (DTI) protocol specification aligns with the Arm System MMU architecture, to define a scalable, distributed messaging protocol for translation services. In an SMMU implementation, there are typically three components:
- A Translation Control Unit (TCU) that performs the translation table walks.
- A Translation Buffer Unit (TBU) that intercepts transactions in need of translation and can cache those translations to reduce transaction latency.
- A PCI Express (PCIe) Root Complex that includes Address Translation Services (ATS).
DTI is a point-to-point protocol where each channel consists of a link between a TBU or PCIe Root Port implementing ATS, and a TCU. The specification outlines two different protocols:
- DTI-TBU: Defines communication between a TBU and a TCU.
- DTI-ATS: Defines communication between a PCIe Root Complex and a TCU.
Issue E of the DTI specification introduces the DTI protocol version 2 (DTIv2). DTIv2 includes support for Armv8.2 features, Memory System Resource Partitioning and Monitoring (MPAM) and more outstanding translation requests.
The AMBA Local Translation Interface (LTI) protocol specification aligns with the Arm System MMU architecture and complements AMBA DTI to improve performance and efficiency for translation services. LTI is a point-to-point protocol and defines the communication between an I/O device and a TBU. It enables devices to directly request a translation for each transaction, while leaving the TBU to manage the TLB. This enables translations to be requested before ordering requirements are met and avoids the need to pass transactions through the TBU. The result is improved performance and reduced silicon area.
The AMBA Low Power Interface (LPI) specification defines Q-Channel and P-Channel interfaces, designed to manage clock and power features of SoC components. Issue D of the AMBA LPI specification adds new optional features, such as the interface parity protection.
|AMBA Protocols||Processors||Interconnect||System IP|
|CHI||Cortex-A||CoreLink CMN Family||CoreLink Memory Controllers|
|ACE||Cortex-A||CoreLink CCI Family|
|AXI||Cortex-A, Cortex-R, Mali Multimedia||CoreLink NIC Family||CoreLink Memory Controllers|
|AHB||Cortex-M||CoreLink NIC Family, Corstone Foundation IP||Corstone Foundation IP|
|APB||Corstone Foundation IP||Corstone Foundation IP|