Maximizing off-chip memory performance, the great CPU and GPU balancing act

10 May 2011

Venue: Webinar
Location: Webinar

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Overview:

Efficient access to shared off-chip memories, especially DRAM, critically influences system performance, power and cost. The available bandwidth to main DDR memory is often the system performance bottleneck. Higher utilisation of bandwidth allows the use of lower frequency memories, with cheaper packaging and narrower ports reducing the number of high performance DDR PHYs. DRAM controllers must also be designed for optimal efficiency with CPU and GPU requirements in mind. Minimising CPU latency is a critical requirement, at the same time as maximising available GPU bandwidth. Balancing system QoS requirements at the same time as maximising memory utilisation is a difficult challenge. This webinar will explain the critical success factors in building processor-to-pads memory systems that meet the demands of complex, high performance SoCs.

What you will learn:

Advanced memory subsystems are becoming vitally important for SoC design
ARM is a leading expert in memory controller and PHY technology
CoreLink DMC-400 is the first AMBA 4 memory controller
- Best in class memory utilization
- Scalable microarchitecture provides roadmap to future memory types: LPDDR3, DDR4 and Wide-IO
ARM has a processor-to-pads system solution with end-to-end QoS

Who Should Attend:

System designers & architects, Soc, ASIC memory system architects, IP core designers