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Siemens Digital Industries Software is driving transformation to enable a digital enterprise where engineering, manufacturing and electronics design meets tomorrow. The Xcelerator portfolio helps companies of all sizes create and leverage digital twins that provide organizations with new insights, opportunities, and levels of automation to drive innovation.

Solution Briefs

  • thumbnail: Validation of Complex Safety Architectures
    Validation of Complex Safety Architectures

    Describes the methodology and flow of how to model fault simulation on SoCs or IP with a combination of hardware and software safety mechanisms. It also describes how Arm used our analysis tool to get accurate metrics early in the safety workflow

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  • thumbnail: Management of Test, Safety, and Security Data at the Edge for ISO 26262
    Management of Test, Safety, and Security Data at the Edge for ISO 26262

    Next Gen. safety and security requires a move from basic hardware controls. Embedded CPU and software-controlled safety architectures are becoming extremely popular. This solution discusses the definition and implementation of a “safety island.”

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Insights

  • Automotive Electronics solutions at AESIN Conference 2021 Blog
    Automotive Electronics solutions at AESIN Conference 2021

    The conference features leading figures in electronics systems innovation, government agencies, and automotive market experts, and Siemens showcased Tessent Embedded Analytics and PAVE 360 as part of a digital twin platform

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  • Addressing Debug Challenges on ARM-based Heterogeneous Multicore SoCs Whitepaper
    Addressing Debug Challenges on ARM-based Heterogeneous Multicore SoCs

    The development and debugging of obstacles introduced by heterogeneous hardware and software system architectures must be addressed by tools and technologies. This white paper discusses this concept leveraging ARM-based SoCs.

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  • Validation of Complex Safety Architectures Webinar
    Validation of Complex Safety Architectures

    This webinar explains the methodology and flow of how to model fault simulation on SoCs or IP with a combination of hardware and software safety mechanisms. It also describes how Arm used analysis to get accurate metrics early in the safety workflow.

    Learn More
  • Veloce Fault App - Accelerate Time to Safety Webinar
    Veloce Fault App - Accelerate Time to Safety

    Companies are facing challenges to meet ISO26262 safety standards due to large gate count SoC designs, full software stack safety mechanisms, and large compute heavy simulation times. This webinar discusses the usage of emulation to satisfy ISO26262.

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  • Automating Physical Mapping on Arm IP with Tessent Arm Tech Talk
    Automating Physical Mapping on Arm IP with Tessent

    In this video, first presented at the 2021 International Test Conference, Arm design engineer Frank Frederick talks about the need for automating physical mapping with Tessent shared bus learning

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  • Leveraging High-quality Test and Embedded Analytics to Secure ICs Blog
    Leveraging High-quality Test and Embedded Analytics to Secure ICs

    There is growing concern over the security of ICs used not just in aerospace and military devices, but also in smart cards, medical, automotive, and datacenters. This blog discusses security strategies deployed to protect ICs.

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  • Tessent Hierarchical ATPG Reference Flow for Arm Cortex-A75 Whitepaper
    Tessent Hierarchical ATPG Reference Flow for Arm Cortex-A75

    The Tessent group of Siemens EDA and Arm jointly developed a reference flow for a hierarchical DFT and ATPG implementation with Tessent for any Arm subsystem based on Cortex A-series IP

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