ARM and Cadence Partner to Implement Industry's First Cortex-A57 64-bit Processor on TSMC 16nm FinFET Process
Ongoing collaboration delivers innovative solutions featuring co-optimization of process, IP and design automation
CAMBRIDGE, United Kingdom, and SAN JOSE, Calif., April 4, 2013 Fulfilling the promise of performance and power scaling at 16 nanometer, ARM (LSE: ARM; Nasdaq: ARMH) and Cadence (NASDAQ: CDNS) today announced details behind their collaboration to implement the first ARM® Cortex®-A57 processor on TSMC’s 16-nanometer (nm) FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan® standard cell libraries and TSMC’s memory macros.
The Cortex-A57 processor is ARM’s highest-performing processor to-date, and is based on the new ARMv8 architecture designed for computing, networking and mobile applications that require high performance at a low-power budget. TSMC’s 16nmFinFET technology is a significant breakthrough that enables continued scaling of process technology to feature sizes below 20nm. This test chip, developed with Cadence’s custom, digital and signoff solutions for FinFET process technology, was a collaboration that resulted in several innovations and co-optimizations between manufacturing process, design IP, and design tools.
“More than ever, success at the leading edge of innovation requires deep collaboration. When designing SoCs incorporating advanced processors, like the Cortex-A57, and optimizing the implementation using physical IP created for FinFET processes, the expertise of our partners is needed,” said Tom Cronk, executive vice president and general manager, Processor Division at ARM. “Our joint innovations will enable our customers to accelerate their product development cycles and take advantage of leading-edge processes and IP.”
The 16nm process using FinFET technology presented new challenges that required significant new development in the design tools. New design rules, RC extraction for 3D transistors, increased complexity of resistance models for interconnect and vias, quantized cell libraries, library characterization that supports new transistor models and double patterning across more layers are some of the challenges that have been addressed in Cadence’s custom, digital and signoff products.
“This major milestone was challenging on all fronts, requiring engineers from ARM, Cadence and TSMC to work as a unified team,” said Dr. Chi-Ping Hsu, senior vice president of R&D for the Silicon Realization Group at Cadence. “Our combined efforts and commitment to innovation will enable our customers to adopt the next generation of IP, process and design technology for designing high performance, low-power SoCs.”
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