The AMBA 4 specifications introduced more interface protocols on top of the AMBA 3 specifications, including ACE, the AXI Coherency Extensions. It addresses high-bandwidth, high-clock-frequency system designs and includes features that make it suitable for high-speed interconnect, typical in mobile and consumer applications.
AMBA AXI and ACE
The AMBA 4 AXI and ACE specification defines a series of protocols, specifically the AXI4, AXI4-Lite, ACE, and ACE-Lite.
The ACE protocol adds three additional channels for sharing data between ACE Manager caches and the cache maintenance hardware control. ACE also adds barrier support to enforce ordering multiple outstanding transactions, minimizing CPU stalls waiting for preceding transactions to complete. Distributed Virtual Memory (DVM) signaling maintains virtual memory mapping across multiple ACE Managers.
The ACE-Lite protocol is a small subset of ACE signals that offer I/O, or one-way coherency, where ACE Managers maintain the cache coherency of ACE-Lite Managers. An ACE-Lite Manager can still snoop ACE Manager caches, but other Managers cannot snoop an ACE-Lite Manager's caches. ACE-Lite also supports barriers.
The AXI4 protocol is an update to AXI3 that enhances the performance and use of the interconnect, when used by multiple managers. It includes the following enhancements:
- Support for burst lengths up to 256 beats.
- Quality of Service signaling.
- Support for multiple region interfaces.
The AXI4-Lite protocol is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. Key features of the AXI4-Lite interface include:
- All transactions are burst length of one.
- All data accesses are the same size as the width of the data bus.
- Exclusive accesses are not supported.
The AMBA 4 AXI-Stream specification defines the AXI4-Stream protocol, which is designed for unidirectional data transfers from transmitter to receiver, with greatly reduced signal routing. Key features of the protocol are:
- Supports single and multiple data streams using the same set of shared wires.
- Support for multiple data widths within the same interconnect.
- Ideal for implementation in FPGA.
The AMBA 4 ATB specification extends the ATB interface and introduces trace synchronization signaling and synchronization request signaling, among other features. ATB is a data-agnostic interface for transferring trace information between components in a trace system. The trace components and bus sit in parallel with the peripherals and interconnect, and provide visibility for debug purposes.
The AMBA 4 APB specification introduces transaction protection and sparse data transfer to the APB interface. APB supports low-bandwidth transactions required to access configuration registers and low-bandwidth data traffic in peripherals. APB is highly compact, low power, and allows configuration and low-bandwidth traffic to be isolated from high-performance interconnects. AMBA 4 APB is fully backward compatible with AMBA 3 APB, allowing the use of existing APB peripherals.
The Q-Channel and P-Channel LPI protocol is designed to manage clock and power features of SoC components. Key features of the LPI protocol are:
- Q-Channel to manage autonomous hierarchical clock gating and simple component power control.
- P-Channel to manage more complex power control features to increase power efficiency.
AMBA 3 is an older generation of AMBA which introduced the Advanced eXtensible Interface (AMBA AXI) protocol. It also introduced the Advanced Trace Buffer (ATB) and extended the APB and AHB protocols.
The AMBA 3 AXI interface specification defines the AXI protocol, which is known as the AXI3 protocol in later generations of AMBA. AXI supports five unidirectional channels with flexible relative timing between them, multiple outstanding transactions and out-of-order data capability. It enables:
- Pipelined interconnect for high-speed operation.
- Efficient bridging between frequencies for power management.
- Simultaneous read and write transactions.
- Efficient support of high initial latency peripherals.
The AMBA 3 AHB specification introduced the AHB-Lite protocol. It enables interconnect between simpler peripherals in a single frequency subsystem, where the performance of AXI is not required. Its fixed pipelined structure and unidirectional channels enable compatibility with peripherals developed for the AMBA 2 AHB specification.
The AMBA 3 ATB specification defines ATB, a data-agnostic interface for transferring trace information between components in a trace system. The trace components and bus sit in parallel with the peripherals and interconnect, and provide visibility for debug purposes.
The AMBA 3 APB specification extended the APB interface defined in the AMBA 2 specification to include wait states and error reporting functionality. APB supports the low-bandwidth transactions necessary to access configuration registers and data traffic through low-bandwidth peripherals.
AMBA 2 is an older generation of the on-chip bus architecture that added the AMBA High-performance Bus (AHB), which is a single clock-edge protocol. It has been widely used on Arm7, Arm9, and Arm Cortex-M designs.