AXI Performance

The latest generation and highest performance AMBA interface is called AXI, Advanced eXtensible Interface. It is targeted at high bandwidth, high clock frequency system designs and includes features which make it very suitable for high speed deep sub-micron interconnect.  The key features and benefits of the AXI protocol are:

Allows implementations to reach higher clock frequencies by making it easy to re-time without losing throughput

• Point-to-point channel architecture

Supports Globally-Asynchronous-Locally-Synchronous (GALS) techniques for large numbers of clock domains with variable frequencies.

• Easy addition of register stages to achieve timing closure

A split channel architecture to increase throughput by taking full advantage of deeply pipelined SDRAM memory systems.

• Burst based transactions with only start address issued
• Issuing of multiple outstanding addresses
• Out of order transaction completion
• Separate address/control and data phases

AMBA 3 Specifications

The AMBA 3 specification defines a set of four interface protocols that, between them, cover the on-chip data traffic requirements from data intensive processing components requiring high data throughput, low bandwidth communication requiring low gate count and power and on-chip test and debug access. The interfaces are:

AMBA 3 AXI Interface

The AMBA 3 AXI interface specification provides the characteristics to support highly effective data traffic throughput. The five unidirectional channels with flexible relative timing between them, and multiple outstanding transactions with out-of-order data capability enable:

• Pipelined interconnect for high speed operation
• Efficient bridging between frequencies for power management
• Simultaneous read and write transactions
• Efficient support of high initial latency peripherals

AMBA 3 AHB Interface

The AMBA 3 AHB interface specification enables highly efficient interconnect between simpler peripherals in a single frequency subsystem where the performance of AMBA 3 AXI is not required. Its fixed pipelined structure and unidirectional channels enable compatibility with peripherals developed for the AMBA 2 AHB-Lite specification.

AMBA 3 APB Interface

The AMBA 3 APB interface specification supports the low bandwidth transactions necessary to access configuration registers in peripherals and data traffic through low bandwidth peripherals. The highly compact and low power interface isolates this data traffic from the high performance AMBA 3 AHB and AMBA 3 AXI interconnects. The AMBA 3 APB interface is fully backwards compatible with the AMBA 2 APB interface allowing existing APB peripherals to be used.

AMBA 3 ATB Interface

The AMBA 3 ATB interface specification adds a data agnostic interface for trace data in a trace system to the AMBA specification. The trace components and bus sit in parallel with the peripherals and interconnect and provide visibility for debug purposes.

AMBA 2 Specifications

The AMBA 3 specification replaces AMBA 2 and should be used for new designs. Existing AMBA 2 peripherals can be used in an AMBA 3 based system. The AMBA 2 specification defines a set of two interface protocols:

AMBA 2 AHB Interface

The AMBA 2 AHB interface specification enables highly efficient interconnect between masters in a single frequency system. This interface includes all of the capabilities of the AMBA 3 AHB interface but also enables the use of arbitration between masters in the construction.

AMBA 2 APB Interface

The AMBA 2 APB interface specification supports the low bandwidth transactions necessary to access configuration registers in peripherals and data traffic through low bandwidth peripherals. The highly compact and low power interface isolates this data traffic from the high performance AMBA 2 AHB interconnect.

Protocol Checkers

Averant SolidPC employs a pre-defined set of technology rules to verify compliance with the AMBA protocol specifications.

ARM Processors