ARM® Physical IP Platforms deliver process optimized IP, for best-in-class processor implementations. These platforms are
comprised of logic libraries, memory compilers and interface IP. Collectively, they provide a powerful suite of design alternatives,
offering System-on-Chip (SoC) designers the ability to balance performance, power, area and manufacturability throughout the
design process. ARM leadership in microprocessor architectures, coupled with its Physical IP Platform, delivers optimal SoC
designs and reduces time-to-market.
ARM Logic family consists of high performance and high density libraries with an enhanced cell set. They generate superior
RTL-to-GDSII results through integration with state-of-the-art EDA tools and flows. The ARM development flow has the industry's
most comprehensive QA and validation procedures, resulting in accurate designs with high manufacturing yields.
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- Embedded Memory Solutions
- High Speed Interface
- Interface Libraries
- Memory Test and Repair
- Logic Libraries
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ARM Logic libraries contain an extensive selection of combinatorial and sequential cells. Library functions are available
in multiple drive strengths to facilitate fast, dense and power-efficient designs. The Logic product line has been synergistically
developed with ARM Cortex™ processors, customer design benchmarks and EDA partners.
To address the challenges of sub-micron dynamic power leakage, the ARM Logic IP family includes Multi-Channel length cells.
These Multi-Channel length libraries allow significant leakage power savings by replacing the HVt implant layer with long
channel length devices, providing better performance, lower voltage and reduced manufacturing costs. Multi-channel libraries
are footprint compatible, enabling effortless cell swapping for leakage/power optimization within standard design flows.
ARM Memory IP provides SoC designers with high quality memories to meet a wide range of performance, power and area requirements.
The Memory family has been defined to specifically target Cortex™ ARM processors in key applications ranging from ultra low
power wireless applications, supporting very low standby power, to optimum power/performance MID applications, needing performance
and long battery life. These features also allow the ARM Memory IP to accelerate operation of high performance, low active
power applications such as high speed consumer netbooks. With an advanced memory architecture combined with an extensive set
of bit cells, the memories support multi-core requirements and enable fast memory access to high performance processors.
ARM Interface IP includes both the General Purpose and High Speed Interfaces (HSI) required to build an SoC pad ring. The
High Speed Interface product family covers a broad range of applications for off-chip memory interfaces (DDR) while the programmable
interface family covers various generic applications needing multi-voltage and voltage tolerant support.
The hard macro HSI DDR IP is designed to be fully compliant with DDR3/2 and LPDDR/2 SDRAM for simplified SoC integration.
The DFI compliant DDR Interface IP enables seamless integration with ARM PrimeCell™ memory controllers for quick RTL-to-GDSII
generation without compromising the power/performance trade-off.
The fully programmable general purpose Interface IP (GPIO) consists of a comprehensive set of building blocks for optimized
pad ring development, supporting a wide range of form factors and package options. The flexible GPIO allows the designer to
reconfigure the IO pads in order to achieve the best throughput and signal quality. All ARM Interface IP is designed to ensure
high SoC reliability meeting industry-standard ESD and latch-up protection levels. The ARM development flow has the industry's
most comprehensive QA and validation procedures.
ARM provides a portfolio of its Physical IP products through web access, with over 3500 products available for download. All products have complete front-end views and .lef files
available for performance and area evaluation. The download products: five memory compilers, two I/O products and one standard
cell library, form the Design Platform upon which SoC teams can accomplish their designs. By providing a common interface
of simulation and tapeout views that does not change for each foundry, ARM helps to enable manufacturing flexibility and reduce
time to market through designer familiarity and high-quality proven IP. All ARM physical IP available for download has been
designed using the same ARM Process-Perfect™ Design Methodology.
Free – Foundry SponsoredThe ARM Free Library Program provides design teams with a wide selection of products optimized for leading foundries' processes at
no charge. The products are high-quality IP which has been licensed from ARM by the specified foundry and made available for download from the ARM website.
Fee based productsThe ARM product family of Physical IP also has many specialty products that are licensed to design teams for a fee. These
products include: high-speed PHY, analog timing IP, general-purpose and specialty I/O, memory compiler and standard cell library
solutions that are optimized for specific processes and foundries to provide unique functionality, density, power and/or area
performance points which are not available in the ARM Free Library Program. These products can be used on the same SoC as
the Free Library Program products to enable superior SoC integration through use of speed-optimized products and density-optimized
products in different areas
All front end views can be downloaded from the website free-of-charge with the Evaluation Design Kits.
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