DDR PHY solutions provide standards based high-speed parallel interface physical solutions meeting key industry standards such as DDR3, DDR2, LPDDR and LPDDR2. Artisan DDR PHY solutions are foundry and process optimized delivering market leading performance, power and area.
ARM Artisan DDR PHY Key Benefits
- Comprehensive memory interface solutions for ARM based SoC in conjunction with ARM Corelink family of memory controllers
- Ensures the highest bandwidth, lowest latency and lowest power configuration without sacrificing flexibility in implementation
- Provides a Time To Market advantage leveraging mature architecture and silicon proven technology
- Lowest risk solutions with a long history of high volume production backed by an experienced support team.
The ARM DDR memory interface IP offers a comprehensive solution for a broad range of application from LPDDR to DDR3. Targeting data rates from 100Mbps up to 1.6 Gb/s data rates, the ARM DDR Interface IP offers the best Power/Performance solution for SoC and ensure robust operation in various packaging and system configurations. The PHY comprises of all analog and digital block required to build the DDR interface. ARM reduces your design risk and ensures seamless integration between blocks and rest of the system.
The DDR interface comes designed to cope with wide range of voltage, temperature, process, package and system variations while ensuring robust signaling between the SoC and off-chip memories. It includes on-die compensation circuitry and supply decoupling to increase power supply noise immunity and reduce jitter.
The ARM DDR interface IP is no stranger to Low Power, deployment of low power operation goes from SoC level all the way down to individual circuit level. Various low power techniques, combined with traffic aware interface, can yield in a significant reduction to the DDR interface power.
