Facilitate Right-First-Time Development of Multi-Processor Designs
AMBA5 CHI (Coherent Hub Interface)specificationis the latest addition to the AMBA family addinga newprotocolfor thehighest performance, highly scalable SoCs required by many server and networking applications.
Issue E of AMBA 4 AXI and ACE protocol specification (Feb 2013) adds new optional properties for AXI ordering, ACE cache behavior and ARMv8 DVM messages for full cache coherency between processors.
For additional information on AMBA Specifications please see the AMBA FAQ Pages.
AMBA enables IP re-use
IP re-use is an essential component in reducing SoC development costs and timescales. AMBA specifications provide the interface standard that enables IP re-use if the following essential requirements are met:
IP re-use requires a common standard while supporting a wide variety of SoCs with different power, performance and area requirements. With its ACE, AXI, AHB and APB interface protocols, AMBA 4 has the flexibility to match every requirement. With AMBA 5 CHI interface ARM extends performance and scalability to many coherent processors.
The multi-layer architecture acts as a crossbar switch between masters and slaves in an AMBA 3 AXI or AHB system. The parallel links allow the bandwidth of the interconnect to support the peak bandwidth of the masters without increasing the frequency of the interconnect.
It is a standard interface specification that ensures compatibility between IP components from different design teams or vendors. The AMBA specifications are available as both a written specification as well as a set of assertions that unambiguously define the interface protocol, thus ensuring this level of compatibility.
The wide adoption of AMBA specifications throughout the semiconductor industry has driven a comprehensive market in third party IP products and tools to support the development of AMBA based systems. The availability of SystemVerilog assertions for AMBApromote this industry wide participation.