Why choose Neoverse CSS N2
Pre-integrated fully validated design
Neoverse CSS N2 delivers CPU, memory, and I/O, engineered as a single architecture.
Ready for the next generation of infrastructure
Adopt the latest Armv9, DDR5, PCIe Gen5, and CXL technologies with a proven, ready-to-deploy design.
Deliver world-class performance per watt
Meet power, sustainability, and lower total cost of ownership goals.
Benefits
Accelerate time to silicon
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A faster path to first silicon:
Accelerate from concept to silicon with a pre-integrated, performance-validated compute subsystem.
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Higher performance with better energy efficiency:
Achieve up to 40% IPC uplift over Neoverse N1, improving performance per watt..
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Reduced integration risk and engineering effort:
Minimize integration challenges with a validated compute foundation, saving engineering time.
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Easier adoption of advanced technologies:
Implement Armv9, DDR5/LPDDR5, PCIe Gen5, and CXL with less integration overhead.
Inside Neoverse CSS N2
The building blocks of Arm Neoverse CSS N2
Arm Neoverse CSS N2 represents a new approach to delivering customized, partner-differentiated silicon to market in record time.
Performance-optimized compute subsystem
Built around Neoverse N2 to deliver high performance for cloud, edge, and networking workloads.
Integrated high-bandwidth connectivity
Combines DDR5/LPDDR5 memory and PCIe Gen5/CXL support for fast, scalable system designs.
Validated multi-core scalability
Offers up to 64 Neoverse N2 cores in a verified subsystem configuration with proven performance.
Accelerated path to production silicon
Provides a pre-integrated design foundation that helps reduce development effort and speed time to market.
Use cases
Where Neoverse CSS N2 is powering real infrastructure
Cloud computing
Cloud customers are experiencing up to 40% improved price performance over comparable traditional architecture-based instances on a broad range of workloads.
Cloud and data center infrastructure
Arm-powered cloud and data center systems deliver the performance, efficiency, and scalability needed to run today’s general-purpose workloads and tomorrow’s AI-driven compute demands. Providers can meet growing performance requirements without compromising TCO or sustainability targets.
Product deep dive
Explore the technical details of the Arm AGI CPU, from individual CPU cores to rack-scale economics and server providers.
Success stories
Success stories powered by Arm Neoverse CSS N2
Optimum price-performance with Microsoft Cobalt
Advancing chiplet innovation for data centers with Novatek
ASICLAND’s design solution with Arm Neoverse CSS N2
Resources
Latest news and resources
- News and Blogs
- Report
Building heterogeneous chiplets with AMBA interconnects
Explore how the new Arm AMBA CHI Chip-to-Chip specification extends coherent interconnect beyond the die, enabling scalable, efficient multi-chip designs while advancing the open chiplet ecosystem.
Key takeaways
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CSS N2 delivers a verified, performance-validated compute foundation that reduces design cycles from years to months.
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With up to ~40% IPC uplift over Neoverse N1, CSS N2 delivers high performance per watt across diverse infrastructure workloads spanning cloud, networking, and edge.
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By providing a pre-integrated compute foundation, CSS N2 reduces integration complexity and late-stage risks, enabling partners to save significant engineering time on the path to first silicon.
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CSS N2 combines Armv9 cores with DDR5/LPDDR5, PCIe Gen5, and CXL in a validated configuration that lets partners adopt advanced technologies with less integration overhead.
FAQs
What is Arm Neoverse CSS N2?
Neoverse CSS N2 is a verified, performance-validated compute subsystem that integrates up to 64 Arm Neoverse N2 cores with DDR5/LPDDR5 memory and PCIe Gen5/CXL I/O to accelerate delivery of infrastructure-class silicon. It provides a customizable, power-optimized foundation for partners.
How does CSS N2 reduce time-to-production silicon?
CSS N2 consolidates CPU clusters, memory, I/O, and system IP into a pre-integrated design with validated performance targets. Partners have reported advancing from design idea to working silicon in approximately 13 months, saving an estimated 80 engineering-years of effort.
What are the performance gains?
In multichip configurations aggregating 256 Neoverse N2 cores at 3.0 GHz, CSS N2 targets an estimated SPECrate®2017_int score of approximately 1,000, indicating high throughput for cloud-scale workloads. Actual results vary by implementation.
Which technologies are supported?
CSS N2 implements leading-edge memory and I/O—including DDR5/LPDDR5, PCIe Gen5, CXL—and is designed to integrate with Arm system IP such as CMN-700, MMU-700, GIC-700, and NI-700 for coherent fabrics, virtualization, and scalable NoCs.