Overview
Designers of AMBA based systems require a high-performance interface between the on-chip AMBA bus interconnect and the off-chip commodity memory devices. ARM provides a range of PrimeCell Memory Controllers to address this requirement. The data-flow characteristics and memory subsystem of each application will be unique, demanding a very high degree of flexibility from the memory controller while cost, area and power drive the need to minimize gate counts. The PrimeCell memory controllers are designed to provide the best balance between these requirements enabling each application to have the optimal memory controllers for its needs. ARM’s expertise and market leadership in AMBA based system design ensure that the PrimeCell peripherals provide a smooth out-of-the-box experience and peace of mind for designers. Benefits
ARM PrimeCell IP is designed to provide solutions that enable licensees to meet their system performance goals whilst minimizing the cost of ownership associated with the acquisition and deployment of 3rd party IP. Amongst the key benefits deliver by the PrimeCell Memory Controllers are: Flexibility: highly configurable IP provides support for the widest range of application, system and memory requirements whilst minimizing the area and power overheads. Integration: with ARM’s design, simulation and analysis solutions - SoC Designer and AMBA Designer – enables the selection of the optimal configuration. Verification & Compatibility: PrimeCell memory controllers are designed and verified for compatibility with ARM’s CPU cores, interconnect fabric and an extensive range of memory solutions. Complete out-of-the-box solution: including all the documentation and infrastructure required for efficient integration into end user systems and design environments.
Portfolio
The PrimeCell memory controllers are implemented to be compatible with a wide range of memory devices. The products we currently offer are shown below. ARM
Product | Description | Gate Count | Technical
Reference
Manual | | PL241 | AHB SRAM/NOR Memory Controller | 32k gates | (904KB PDF) | | PL242 | AHB NAND & SDRAM Memory Controller | 138k gates | (1MB PDF) | | PL243 | AHB SRAM/NOR & SDRAM Memory Controller | 146k gates | (2MB PDF) | | PL244 | AHB NAND & DDR Memory Controller | 157k gates | (1MB PDF) | | PL245 | AHB SRAM/NOR & DDR Memory Controller | 165k gates | (2MB PDF) | | PL340 | AXI Configurable Dynamic Memory Controller | 60k-110k gates1 | (581KB ZIP) | | PL351 | AXI Configurable Single NAND interface Memory Controller | 18k-75k gates1 | (1MB PDF) | | PL352 | AXI Configurable Single SRAM interface Memory Controller | 18k-75k gates1 | (1MB PDF) | | PL353 | AXI Configurable SRAM & NAND interface Memory Controller | 18k-75k gates1 | (1MB PDF) | | PL354 | AXI Configurable Dual SRAM interface Memory Controller | 18k-75k gates1 | (1MB PDF) |
Note 1 - Gate counts for configurable PrimeCells show a range of typical, usable configurationsThe SRAM interface of the PL35x family is capable of supporting a wide range of memory products including synchronous or asynchronous SRAM, Pseudo-Static RAM (PSRAM, Cellular RAMTM, UtRAM, CosmoRAM), NOR Flash and NAND Flash devices with SRAM interfaces. For more information on these, or other AMBA devices, please contact your local ARM representative. Alternatively you can submit an email enquiry here. Back to Top | 
