High-Performance Cache Controller

The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm AXI processors, including the Cortex-A5, Cortex-R4, Cortex-R5, Arm11MPCore, Arm1176, Arm1156, and the Mali-200 graphics processor.

Features and Benefits

Improve Processor Performance

Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip.

Provide Power Efficiency

Memory access on-chip typically uses much less power compared to going off-chip, and free up bandwidth.

Easy Integration

CoreLink level 2 cache controllers are designed to match processor requirements and easily integrate into AMBA AXI or AHB interconnects.

Use Cases

Where Innovation and Ideas Come to Life

詳細

ヘルスケア

健康中心のアプリケーション全体で、コストを削減してケアを改善します。血糖値モニターや心拍数トラッカーなど、予防ケアにおける革新的なアプリケーションのサポート。

Talk with an Expert

Looking for additional resources to help you design Arm-based SoCs? Talk to an Arm expert.

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L2C-310 Resources

Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.