High-Performance Cache Controller

The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm AXI processors, including the Cortex-A5, Cortex-R4, Cortex-R5, Arm11MPCore, Arm1176, Arm1156, and the Mali-200 graphics processor.

Features and Benefits

Improve Processor Performance

Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip.

Provide Power Efficiency

Memory access on-chip typically uses much less power compared to going off-chip, and free up bandwidth.

Easy Integration

CoreLink level 2 cache controllers are designed to match processor requirements and easily integrate into AMBA AXI or AHB interconnects.

Use Cases

Where Innovation and Ideas Come to Life


Talk with an Expert

Looking for additional resources to help you design Arm-based SoCs? Talk to an Arm expert.

Contact Us
Related Products and Services

Explore More Options and Features

Cortex Processors

Arm processors include the ultra-low power Cortex-M series, real-time response Cortex-R series, and the high performance Cortex-A series.


Arm MaliメディアIPは、スマートフォン、タブレット、テレビ、ウェアラブルなど、多数の成長を続けるモバイルおよびコンシューマデバイスで高性能でエネルギー効率の高いメディア処理を提供します。

CoreLink Interconnect 

Arm CoreLink Interconnect provides the components and the methodology to build SoCs based on the latest AMBA specifications, maximizing the efficiency of data movement and storage, and delivering the required performance.



Socrates System Builder

Arm Socrates System Builderツールは、Arm IPの選択、構成、作成、およびシステムアセンブリをガイドし、Armベースのシステムを迅速かつ簡単に構築します。

L2C-310 Resources

Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.