The challenges of SoC integration
There are many problems facing teams producing today’s complex SoC designs. Creating initial SoC stitching or netlists can take weeks, or even months. Despite all this effort, many IP integration bugs are found through formal analysis or simulation, and some are never found at all. It is challenging to verify that IP is integration-ready, as many of these bugs relate to inconsistent IP configurations. Solving these problems can cause major delays to designs and the overall product delivery, leading to losses in revenue and a huge rise in costs.
Highly dependent system IP, such as interconnect and debug, is also on this critical path in the design cycle, making the job of designing the SoC by non-experts very difficult. Out-of-date documentation and interoperability with EDA vendor tools can also cause issues integrating 3rd party or custom IP with the SoC design.
The ARM Solution - ARM IP Tooling, which ensures IP standardization, configuration, and intelligent integration.
Socrates Design Environment
The ARM Socrates DE standardizes, configures, and intelligently integrates IP with ARM IP to create a SoC. Architects and designers can standardize any IP into IEEE1685-2009 to be integration-ready, configure standardized IP, and intelligently integrate IP quickly and efficiently.
ARM CoreSight™ Creator guides users through the configuration and creation of an optimized and viable CoreSight Debug & Trace subsystem. Its rules-based methodology removes the need for CoreSight expertise, and enables partners to generate a CoreSight subsystem in days, with minimal engineering interaction.
ARM CoreLink™ Creator is a tool that guides users through the configuration and creation of an optimized and viable CoreLink Interconnect. Its rules-based design methodology generates IP components, stitches them together, and validates the top level.