Dynamic Memory Controllers and Static Memory Controllers
AMBA Dynamic and Static Memory Controllers provide the ideal interface to off-chip memory for systems with Cortex™ (A,R) and Mali™ processors. They have been designed, verified and benchmarked in conjunction with ARM processors and AMBA interconnect products to enable designers of ARM processor-based systems to implement the optimal digital highway for their application.
There are controllers for the ARM AMBA AXI and AHB bus protocols, providing interfaces to the dynamic and static memories used in these designs.
The current products are the 3rd generation of memory controllers developed by ARM, highlighting our experience and commitment to delivering the solutions our Partners need.
AMBA Memory Controllers:
- Deployed by more than 70 licensees into a wide range of applications including mobile, consumer, networking and embedded products.
- Provide low risk, high efficiency off-chip memory interface for ARM processor-based SoCs.
- Service requests from multiple low-latency and high-bandwidth masters in conjunction with AMBA Interconnect to ensure Quality of Service
- Order memory transactions to maximize utilization of the memory bus
- Manages memory accesses and power modes to provide optimal energy efficiency
Interfaces to DDR, LPDDR, DDR2, LPDDR2, NAND Flash, NOR Flash and more
AMBA Memory Controllers are designed to work with industry standard interfaces to ensure easy integration into systems. ARM is deeply engaged with the bodies and consortiums defining those standards including JEDEC, SPMT, MIPI and DFI.
