CoreLink Memory Controllers

Dynamic Memory Controllers and Static Memory Controllers

CoreLink Dynamic and Static Memory Controllers provide the ideal interface to off-chip memory for systems with Cortex™ and Mali™ processors.  Designed, verified and benchmarked in conjunction with ARM processors and AMBA interconnect products, they enable designers of ARM processor-based systems to implement the optimal digital highway for their application.

 The diagram below shows a CoreLink DMC-400 in a CoreLink 400 system:

There are also controllers for the ARM AMBA AXI and AHB bus protocols, providing interfaces to the dynamic and static memories used in AMBA3 AXI and AMBA AHB designs. 

CoreLink Memory Controllers:

• Deployed by more than 70 licensees into a wide range of applications including mobile, consumer, networking and embedded products.
• Provide low risk, high efficiency off-chip memory interface for ARM processor-based SoCs.
• Service requests from multiple low-latency and high-bandwidth masters in conjunction with AMBA Interconnect to ensure Quality of Service
• Order memory transactions to maximize utilization of the memory bus
• Manages memory accesses and power modes to provide optimal energy efficiency

4th Generation DMC-400 Interfaces to LPDDR2 and DDR3

The CoreLink DMC-400 Dynamic Memory Controller provides support for multiple channels to interface to the full specification of either DDR3, DDR2 or LPDDR2 DRAM. The DMC-400 offers excellent integration with the CoreLink 400 interconnect products (CCI-400 and NIC-400) via AMB3 AXI or AMBA 4 interfaces, sharing QoS mechanisms and power management.

3rd Generation AXI Memory Controllers Interface to DDR2, LPDDR, DDR, NAND Flash, NOR Flash and more

CoreLink Memory Controllers are designed to work with industry standard interfaces to ensure easy integration into systems.  ARM deeply engages with the bodies and consortiums defining those standards including JEDEC, SPMT, MIPI and DFI.