CoreLink DMC-34x Dynamic Memory Controllers

CoreLink DMC-34x Dynamic Memory Controllers Image (View Larger CoreLink DMC-34x Dynamic Memory Controllers Image)
CoreLinkCoreLink™ Dynamic Memory Controllers (DMC) are designed for efficient operation with ARM CPUs, media processors and systems IP. They provide highly optimized arbitration and scheduling algorithms to maximize use of the available DRAM bandwidth. At the same time, they manage the latency requirements of the initiators through Quality of Service Quality of Service (QoS) controls within the system.

Why choose a CoreLink Dynamic Memory Controller?

The interface to dynamic memory is one of the key control points in a SoC that can critically affect system performance. To ensure that the interface efficient implementation, it is important to choose a solution that has been carefully designed to work with both the on-chip AMBA interconnect and the off-chip DRAM memory protocol.

DMC sits a key system control point

ARM has a long history of designing memory controllers for AMBA-based systems. Working closely with the CPU and media processor teams and ARM's network of Partners, the current product offerings represent the 3rd generation of controllers. 

The DMC-34X and PL24X families of controllers have been developed to provide the optimal compatibility with the network interconnect solutions to enable the performance demanded by Cortex-ACortex-R and Mali processors.

Verification and Benchmarking

Understanding the performance and functionality of the memory controller in a system context is critical to the specification and development of the controller. The system level verification and benchmarking performance ensures the delivery products that have been fully qualified alongside the cores and on-chip interconnect. These results then drive the specifications of both current and future memory controllers. They ensure our Partners have the efficient, low-risk, easy to integrated solutions that enable development to proceed smoothly meeting performance goals and delivering time to market.

AXI Dynamic Memory Controllers for DDR, DDR2, LPDDR and LPDDR2

The CoreLink DMC-34X family of products provide an interface between AMBA AXI interconnects and DRAM.

 Product Memory Types Supported  Notes 
DMC-340  SDR, DDR, LPDDR, eDRAM  LPDDR support includes NVM
DMC-341  DDR2  
DMC-342  LPDDR2  S2A, S2B, S4A, S4B

DMC-34X controllers are configurable for a wide range of system settings. Refer to the specifications section for an overview of the configuration options.

AHB Memory Controllers

The PL24X family products provide an interface between AMBA AHB interconnects and DRAM. These are hybrid controllers also providing an interface to non-volatile memory systems.

 Product  DRAM Support  Non-Volatile Support AHB Ports
 PL242  SDR  NAND Flash 4
 PL243     SDR  NOR Flash and SRAM 4
 PL244  DDR  NAND Flash 6
 PL245  DDR  NOR Flash and SRAM 6

Other combinations of memory can be supported by using a combination of the NIC-301 interconnect product with DMC-34X and SMC-35X memory controllers.

CoreLink Dynamic Memory Controllers for AMBA AXI

Features and Benefits

Feature  Benefits 
Configurable through AMBA Designer Optimize the controller for a broad range of applications, system requirements and minimize area.
Quality of Service Prioritizes requests for latency sensitive masters.
Request Arbitration Orders memory requests to maximize the use of available memory bus bandwidth.
AXI native interface Native support for AMBA AXI enables data packing/unpacking; out-of-order writes and burst termination for efficient data management.
Power Management Manages DRAM and controller power modes to minimize power consumption.
Auto pre-charge and active fast-path Auto pre-charge enables support for data striping; active fast-path minimizes fixed latency.
ECC Built-in error correction for error sensitive applications.
DFI Support for the standardized DDR PHY interface eases integration with compatible PHYs such as those available from ARMs PIPD division.

Configurable Options

The DMC-34X family of controllers are highly configurable to support a wide range of application types. Configuration options (where applicable) include the following options.

Option Benefit
Arbitration queue depth Deeper queues can improve performance; minimizing queue depth reduces gate count.
Read & write data queues Configure to match the system requirements (number of masters, burst sizes, outstanding transactions).
Bus widths Manages packing and unpacking between differing system and memory bus widths.
Memory interfaces Supports a wide range of requirements including chip selects, clock enables and exclusive accesses.

Power, performance and area

As configurable soft IP the power, performance and area will depend on such factors as the process technology, design flow and configuration options selected.  The IP, designed for low power, meets the performance goals of AXI systems and memory specifications. The controllers support the full range of the JEDEC specifications for the appropriate memory type.

The area, optimized by setting of configuration parameters to match the system requirements, removes unnecessary overhead from the final implementation.

CoreLink Dynamic Memory Controllers: Related Products

The DMC-34X and PL24X memory controllers have designed compatibility with the ARM IP product portfolio.

CoreLink DMC Products

Related ARM IP Products

CoreLink DMC-520 CoreLink CCN-504 High-performance system IP solution for many-core applications
CoreLink DMC-400 CoreLink NIC-400,
CoreLink CCI-400
Working together to manage the latency requirements of initiators through Quality of Service (QoS) controls within the system
Dynamic Memory Controllers
(DMC-340, DMC-341, DMC-342, PL242, PL243, PL244, PL245)
AMBA Designer Configuration and stitching
VPE Performance exploration and functional verification
NIC-301, QoS-301, ADK AMBA AXI and AHB interconnect
Cortex-A, Cortex-R, ARM11, ARM9 CPU processors
Mali Graphics Processors and Video Engines Multimedia processors
Level 2 Cache Controller (L2C-310)DMA Controllers (DMA-330), System controllers
SMC-35X     Static memory controllers
DDR PHYs           Memory interface PHYs




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