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CoreLink DMC-400 Dynamic Memory Controller

CoreLink DMC-400 Dynamic Memory Controller Image (View Larger CoreLink DMC-400 Dynamic Memory Controller Image)
The CoreLinkTM DMC-400 Dynamic Memory Controller provides support for multiple channels to interface to the full specification of either DDR3, DDR2 or LPDDR2 DRAM. The CoreLink DMC-400 offers excellent integration with the CoreLink 400 interconnect products (CCI-400 and NIC-400) via AMBA3 AXI or AMBA 4 interfaces, sharing QoS mechanisms and power management.
 


CoreLink DMC-400 Dynamic Memory Controller

Optimized and efficient access to the DRAM is critical to the performance of any SoC. As the number of processing elements on a chip increases, the demand for data increases.  As the DRAM technology evolves, the frequency of operation rises, and the complexity of making best use of the DRAM increases. Managing the differing demands of multiple processing elements while trying to make optimum use of DRAM is the challenge faced by a Dynamic Memory Controller.

The CoreLink DMC-400 is ARM's fourth generation of Memory Controller. CoreLink DMC-400 has been designed to meet the needs of different masters in the system while trying to achieve maximum bandwidth from the DRAM. CoreLink DMC-400 is a key part of ARM's End-to-End Quality of Service (QoS) scheme which includes features distributed across both Interconnect and Memory Controllers.

The CoreLink DMC-400 has an advanced QoS based scheduling and arbitration algorithm. QoS values defined by the system are used to re-order transations to be sent to memory.  The DMC arbitration uses bank and row status to aggressively re-order transactions to optimise both bank parallelism and in row hits.

The CoreLink DMC-400 has been specified, designed and validated in conjunction with ARM's CoreLink-400 System IP.


High bandwidth, low latency DMC-400

ARM has developed a DMC performance methodology against which to specify, design, develop and test Memory Controller performance. 

DMC-400 acheieves greater than 90-percent of theoretical maximum DRAM bandwidth across a wide range of test scenarios.

QoS mechanisms in DMC-400 ensure critical masters can achieve minimum latency.

 


System Interfaces  1, 2 or 4 ACE-Lite interfaces (ACE-Lite, AXI4 or AXI3 can be connected) 
System Data Width  64, 128 or 256 bit ACE-Lite
Configuration APB interface
Memory Interfaces  1 or 2 Memory interfaces to connect to independent channels of DRAM via DFI interface
Memory Types  DDR3, DDR2 or LPDDR2 
Memory Width 16, 32 or 64 bit DRAM per memory interface
ECC Optional SECDED ECC supported to DRAM
QoS QoS based scheduling algorithm, QVN (Virtual Networks) to avoid blocking
Low Power All DRAM power modes supported and hierarchical clock gating throughout the DMC 

Cortex Processors

DMC-400 can be used to provide memory access in systems built around all ARM Cortex Processors

Graphics Processors

DMC-400 can be used to provide memory access in systems built around all ARM Graphics Processors.

CoreLink System IP

DMC-400 is part of the CoreLink 400 series of System IP.

Physical IP

ARM Artisan provide standard cell library and compiled RAM for implementation of DMC-400.  ARM also provides DDR PHY IP that has been designed and verified with DMC-400.


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