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IP Tooling

Simplifying the Way Our Partners Configure & Integrate System IP

ARM® IP Tooling provides System IP Tooling to hardware, software and verification teams to deliver fully integrated System IP. It is the only fully integrated solution to integrating ARM System IP.

The IP Tooling solutions by ARM are:

ARM Socrates Design Environment

The ARM Socrates DE standardizes, configures and intelligently integrates IP with ARM IP to create a SoC. Architects and Designers can standardize any IP into the IEEE1685-2009 standard to be ‘integration-ready’, configure standardized IP and intelligently integrate IP together quickly and efficiently.

CoreSight Creator

ARM CoreSight Creator is a tool that guides users through the configuration and creation of an optimized and viable CoreSight Debug & Trace subsystem. Its rules-based methodology removes the need for CoreSight expertise and enables partners to generate a CoreSight subsystem in days with minimal engineering interaction.

CoreLink Creator

ARM CoreLink Creator is a tool that guides users through the configuration and creation of an optimised and viable CoreLink Interconnect. Its rules-based design methodology generates IP components, stitches them together and validates the top level.

AMBA Designer

AMBA Designer makes it faster to configure and connect ARM Cortex™ A, R and M class processors, Mali™ graphics hardware and AMBA IP, and applies captured designer knowledge when specifying configuration parameters in order to reduce risk.

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The reality of IP integration

There are many problems facing design teams in todays complex SoC designs. Creating initial SoC stitching/netlists can take weeks or even months, and even after all this effort many IP integration bugs are found through formal analysis or simulation, and some are never found at all. Due to this, it is difficult to qualify IP and 'integration ready' as many of these bugs are are to do with inconsistent IP configurations. Solving these problems can cause major delays to designs and the overall product, leading to losses in revenue and a huge rise in costs.

Higly dependant System IP such as interconnect and debug is also on this critical path in the design cycle, making the job of designing the SoC to non system IP experts a very difficult task. It is also currently very difficult to integrate 3rd party IP/custom IP within the SoC. The disconnect is obvious around the area of documentation which is never up to date, and the interopertion with EDA vendor tools.

The ARM Solution - ARM IP Tooling that ensures IP Standardization, Configuration & Intelligent Integration

 

Socrates

ARM Socrates Design Environment

Socrates DE Design Environment is a tool that ensures IP is ‘integration-ready’, configures IP that is consistent with other IP in the system, intelligently integrates IP, assembling a viable system in weeks, not months. Using Socrates DE, Architects and Designers can standardize any IP into the IEEE1685-2009 standard to be ‘integration-ready’, configure standardized IP and intelligently integrate IP together quickly and efficiently. Architects and Designers can visualize each stage of the design as well as validate the viability and quality using Design Rule Checks. RTL and the design specification can be generated automatically.

Features

  • Enabling IP Standardization. Socrates uses an IP-XACT design environment to standardize IP in the IP-XACT standard.
  • Fast IP Configuration. Socrates has guided configuration of system IP that is correct-by-construction.
  • Intelligent IP Integration. Socrates allows intelligent and automated IP integration utilizing system meta-data and ARM engineering know-how.
  • Better Design Rule Checks. Socrates runs design rule checks to ensure that the system is viable.

ARM CoreSight Creator Debug & Trace System IP Tooling

ARM CoreSight Creator is a tool that guides users through the configuration and creation of an optimized and viable CoreSight Debug & Trace subsystem. Its rules-based methodology removes the need for CoreSight expertise and enables partners to generate a CoreSight subsystem in days with minimal engineering interaction.

Features

  • High Level Specification based on IP-XACT that identifies and defines the typical interfaces needed to generate a CoreSight subsystem
  • Automatic Micro-Architecture Synthesis of a CoreSight debug and trace subsystem
  • Multiple Design Rule Checks ensure the system is viable and valid, making it correct by construction
  • Deliverables such as RTL, testbenches and test cases are generated at the click of a button

 

ARM CoreLink Creator Interconnect System IP Tooling

ARM CoreLink Creator is a tool that guides users through the configuration and creation of an optimized and viable CoreLink Interconnect. This enables faster, easier design that produces a better quality interconnect. CoreLink Creator works in conjunction with the CoreLink NIC-450 to provide the requirements to generate and stitch multiple CoreLink NIC-400’s and the components required to connect them across power and voltage domains.

Features

  • High Level Specification based on IP-XACT that identifies and defines the typical interfaces needed to generate a CoreLink Interconnect
  • Automatic Micro-Architecture Synthesis of a CoreLink system interconnect
  • Multiple Design Rule Checks ensure the system is viable and valid, making it correct by construction
  • Deliverables such as RTL, testbenches and test cases are generated at the click of a button

 

ARM Socrates Spinner

Socrates Spinner App is an award-winning tool that specifies the complete I/O layer, auto-generates multiple design views and enables seamless integration of the I/O fabric with the rest of the system.

Socrates Spinner simplifies and automates the specification and verification of the I/O subsystem, slashing development schedules, enhancing inter-team communications and virtually eliminating the risk of I/O bugs.




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