CoreLink DMC-520 Dynamic Memory Controller for Enterprise

CoreLink DMC-520 Dynamic Memory Controller for Enterprise Image (View Larger CoreLink DMC-520 Dynamic Memory Controller for Enterprise Image) The CoreLinkTM 500 series introduces the 5th generation, CoreLink DMC-520 Dynamic Memory Controller specifically designed to provide an optimal solution for enterprise applications including servers and network infrastructure. The CoreLink DMC-520 uses the AMBA® 5 CHI (Coherent Hub Interface) specification to connect directly to the CoreLink CCN-502, CCN-504, CCN-508, and CCN-512 Cache Coherent Network interconnects . The CoreLink DMC-520 provides a high bandwidth interface to shared off-chip memory, such as DDR4, DDR3 and DDR3L DRAM along with full DIMM support. Enterprise class RAS (Reliability, Availability and Serviceability) features such as SECDED and enhanced symbol-based ECC for x72 DRAM, TrustZone security and End-to-End QoS are integral components of this new memory controller. CoreLink DMC-520 uses the DFI 3.1 interface to enable integration with a DFI-compliant DDR PHY and has proven interoperability with various customer and 3rd party PHYs. 

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CoreLink DMC-520 Dynamic Memory Controller

Optimized and efficient access to the DRAM is critical to the performance of any Enterprise SoC. As the number of processing elements on a chip increases so, the demand for data increases. As the DRAM technology has evolved to DDR4, the frequency of operation rises, but also the complexity of making best use of the DRAM increases. Managing the differing demands of multiple processing elements while trying to make optimum use of DRAM is the challenge faced by a Dynamic Memory Controller.

The CoreLink DMC-520 is ARM's fifth generation of Memory Controller. CoreLink DMC-520 has been designed to meet the needs of an Enterprise system based around a Cache Coherent Network product from ARM. CoreLink DMC-520 is a key part of ARM's End-to-End Quality of Service (QoS) scheme that includes features distributed across both Interconnect and Memory Controllers.

The CoreLink DMC-520 has an advanced QoS based scheduling and arbitration algorithm. QoS values defined by the system are used to re-order transitions to be sent to memory. The DMC arbitration uses bank and row status to aggressively re-order transactions to optimize both bank parallelism and in row hits.

The CoreLink DMC-520 has been specified, designed and validated in conjunction with ARM's CoreLink 500 System IP.


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