ARM Debug Interface (ADI)
ADIv5 defines a standard debug interface for debug components in an embedded System on Chip (SoC), the ADI architecture encompasses:
- Embedded core debug functionality.
- System debug functionality
This specification is written for system designers and engineers who are specifying, designing or implementing a debug interface to the ADIv5 architecture specification.
ARM Debug Interface (ADI) Documentation
Embedded Trace Macrocell™ Architecture Specification
An Embedded Trace Macrocell (ETM) is a real-time trace module providing instruction and data tracing of a processor. An ETM is an integral part of an ARM CoreSight debug and real-time trace solution.
This specification describes the ARM Embedded Trace Macrocell (ETM) architecture. All ETMs conform to a version of this architecture that covers the following areas of functionality:
- The Programmer’s Model
- The Trace Port Protocol
- The Physical Interface
Embedded Trace Macrocell™ Architecture Specification
CoreSight Program Flow Trace™ Architecture Specification
A Program Trace Macrocell (PTM) is a real-time trace module providing instruction tracing of a processor. A PTM is an integral part of an ARM CoreSight debug and real-time trace solution.
This specification describes the Program Flow Trace Macrocell ™ (PTM) architecture. All PTMs conform to a version of this architecture that covers the following areas of functionality:
- The Programmer’s Model
- The Trace Port Protocol
- The Physical Interface
CoreSight™ Program Flow Trace™ Architecture Specification
CoreSight Architecture Specification
The CoreSight architecture provides a set of standard interfaces and programmer model views enabling partners to define CoreSight components and integrate them within the CoreSight infrastructure.
CoreSight™ Architecture Specification
High Speed Serial Trace Port (HSSTP) Architecture Specification
The HSSTP architecture specification specifies a Serial Transmit Port (STP) as a replacement for existing parallel data output port suitable for transmitting high bandwidth data off-chip such as from the CoreSight solution. HSSTP specification lower ASIC pin count, increase possible bandwidth and, in some cases, reduce the silicon area.
High Speed Serial Trace Port (HSSTP) Architecture Specification
