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Reference Methodologies

ARM continues to work closely with leading EDA companies to develop Reference Methodologies for implementation flows (RMs) that enable ARM licensees to customize, implement, verify and characterize soft ARM processors for their chosen process technologies. The reference methodologies provide a predictable route to silicon, and a basis for custom methodology development, using both logical and physical synthesis technologies.

Since June 2006, ARM has been able to deploy processor RMs that additionally contain ARM Physical IP front-end library views, and pre-compiled RAMs in support of a wide range of ARM processor products - please click on the link in the AppNotes column in the table below for processor-specific library information. This enhances the ability of the RMs to demonstrate processor implementation flows and provides a far more complete reference solution than previously offered. The RMs are free on request for those processors to which Partners have current contractual entitlements.

Supported Reference Methodologies:

 
 
 


The design of ARM Reference Methodologies provides ARM Partners with a simple, deterministic and rapid route from RTL to GDSII. In working closely with each of the industry's leading EDA companies, we have been able to bring years of engineering experience to the problem of turning soft IP into IP hardened for a particular silicon process, and then modeling it so that it can be deployed as a library-level component in today's high-performance system chips.

The result is a set of methodologies that ARM licensees can be sure provide a sound platform for their own customizations and a flow that proven with today's leading tools and IP.

Since the Reference Methodology program is one of continuous improvement, licensees can be confident that their chosen methodology will always be the expression of best practices for ARM soft IP and EDA tools.


The ARM Reference Methodology is a very useful aide to enabling the best QoR and TAT for your design. In addition, ARM and its EDA partners also collaborate on other projects that will assist you to get the best from your design, including information about low power techniques for example. Here some other resources you may find useful:-

Cadence

The Power Forward Initiative (PFI) has published a comprehensive Practical Guide to Low-Power Design - User Experiences with CPF. The guide details low power challenges, techniques, design methodology, and design team experiences - including how to speed your designs to market using Cadence flow.

Magma

An useful Compendium of articles by Magma Design Automation from the ARM Information Quarterly (IQ) Magazine, a publication of ARM and Convergence Promotions, covers subjects such as hierarchical design for the ARM Cortex-A9 and related issues.

Synopsys

Video - Design for Power Gating - And What UPF Can, and Cannot, Do for You - Dave Flynn, ARM Fellow

Power gating is a valuable technique for reducing standby power in portable applications and supports power-rail switching of subsystems to cut leakage power.Originally recorded March 17, 2009 at SNUG San Jose in Santa Clara, Calif., apply to download this very useful video.

The "Low Power Methodology Manual" (LPMM) is a comprehensive and practical guide to managing power in system-on-chip designs, critical to designers using 90-nanometer and below technology. Find out more by applying to download the LPMM book.

 

Describing low-power design intent with a low power description language such as the Unified Power Format (UPF) can help improve complex integrated circuits design, verification and implementation methodology. Find out more about Accellera and UPF by downloading the UPF Solutions Guide 


Processors Product App Note Cadence Magma Synopsys

Cortex-A8™

AT490

 

Encounter 7.1.1

Blast 5.0

Galaxy 2007.03

Cortex-A9™

AT395

 

Encounter 7.1.1

Talus 1.0

Galaxy 2008.09

Cortex-A9MP™

MP004

 

Encounter 7.1.1

Talus 1.0

Galaxy 2007.12

Cortex-R4(F)™

AT430

Encounter 7.1.2

Blast 5.0

Galaxy 2008.09

Cortex-M3™

AT420

Encounter 7.1.2

Blast 5.0

Galaxy 2008.09

ARM1136J-S™

AT310

 

Encounter 4.2

 

Galaxy 2007.03

ARM1136JF-S™

AT260

 

Encounter 4.2

 

Galaxy 2007.03

ARM1156T2-S™

AT370

 

Encounter 4.2

 

Galaxy 2007.03

ARM1156T2F-S™

AT360

 

 

 

Galaxy 2007.03

ARM1176JZ-S™

AT390

Encounter 4.2

 

Galaxy 2007.03

ARM1176JZF-S™ (IEM)

AT380

Encounter 7.1.2 (Encounter 6.2)

Blast 5.0

Galaxy 2008.09 (Galaxy 2005.09)

ARM11 MPCore™

MP002

 

Encounter 6.2

Blast 5.0

Galaxy 2007.03

ARM926EJ-S™

AT230

Encounter 7.1.2

Talus 1.0

Galaxy 2008.09

ARM946E-S™

AT210

 

 

Blast 5.0

Galaxy 2007.03

ARM966E-S™

AT200

 

 

 

Galaxy 2008.09

ARM968E-S™

AT410

 

 

 

Galaxy 2004.06

ARM7TDMI-S™

AT080

 

 

 

Galaxy 2008.09

ARM7EJ-S™

AT290

 

 

 

Galaxy 2004.06

ARM1026EJ-S™

AT350

 

 

 

Galaxy 2004.06

CoreSight™ ETM9™

TM910

 

 

 

Galaxy 2007.03

CoreSight™ ETM11™

TM920

 

Encounter 7.1.2

 

Galaxy 2007.03

L2 Cache Controller

PL310

 

Encounter 7.1.2

 

 

Program Trace Macrocell for Cortex-A9

TM950

 

Encounter 7.1.2

Talus 1.0

Galaxy 2007.12

Supported Libraries Various, from ARM Physical IP TSMC180G down to TSMC65GP /LP Various, from ARM Physical IP TSMC13G down to TSMC65GP /LP Various, from ARM Physical IP TSMC180G down to TSMC65GP /LP

Maximise


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