Presenting the Next Generation of Mobile Processing
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The performance demanded by smartphones and tablets is increasing at a much faster rate than technology improvements in battery capacity and the advances in semiconductor process nodes. The need for higher performance directly conflicts with the desire for longer battery life. The solution to this lies beyond process technology and traditional power management and requires further innovation in mobile SoC design. big.LITTLE is one of many power management technologies employed by ARM to save power in mobile SoCs. It works in tandem with Dynamic Voltage and Frequency Scaling (DVFS), clock gating, power gating, retention modes, and thermal management to deliver a full set of power control for the SoC.
big.LITTLE technology takes advantage of the dynamic usage pattern for smartphones and tablets. Periods of high processing intensity tasks such as initial web page rendering and game physics calculation alternate with typically longer periods of low processing intensity tasks such as scrolling or reading a web page, waiting for user input in a game, and lighter weight tasks like texting, e-mail and audio. The graph below (Fig.1) shows the CPU residency at various DVFS frequency states in a big.LITTLE SoC, with all the relevant power management techniques in operation. It shows the usage of the big CPU cores in burst mode (i.e. for short durations at peak frequency) while the majority of runtime is managed by LITTLE cores at moderate operating frequencies.
Fig 1: The distribution of per-core DVFS Frequency States during Web Browsing with Audio Playback
Innovative power-saving techniques are required to sustain the pace of innovation in mobile through performance increases in the same power footprint. Many of the mobile use cases exhibit behavior like that shown in the graph above, presenting an ideal opportunity for big.LITTLE technology to save power while also delivering peak-performance in modern mobile devices.
big.LITTLE Processing – How does it work?
The high performance and high efficiency CPU clusters are connected through a cache coherent interconnect fabric such as the ARM CoreLink™ CCI-400.This hardware coherency enables the same view of the memory to both the big and LITTLE CPU clusters. The processors look like one multicore CPU to the operating system (OS). User space software on a big.LITTLE SoC is identical to the software that would run on a standard Symmetrical Multi-Processing (SMP) CPU.
How does the work get scheduled to the right processor?
Global Task Scheduling (GTS) gives the OS awareness of the big and LITTLE processors, and the ability to schedule individual threads of execution on the appropriate CPU core based on dynamic run-time behavior. ARM has developed a kernel space patch set based on GTS called big.LITTLE MP that keeps track of load history as each thread runs, and uses the history to anticipate the performance needs of the thread next time it runs. This software is in operation on the use case graph above (Fig. 1) and in the measured results below (Fig. 2), where big.LITTLE technology is delivering energy savings as high as 75% for the same or higher delivered performance.
Fig. 2: Measured CPU and SoC power savings on a Cortex-A15 MP4∙Cortex-A7 MP4 big.LITTLE MP SoC relative to a Cortex-A15 MP4 SoC
The latest CPUs from ARM, including the ARMv8 architecture-based Cortex®-A53 and Cortex-A57, fully support big.LITTLE and can be deployed using similar software. The CPU clusters are connected using the same CoreLink CCI-400 cache coherent interconnect in big.LITTLE SoCs. The big.LITTLE MP software is written to allow a migration to ARMv8-A architecture support, with updated ARMv8 architecture patch sets available for SoC launches with the Cortex-A50 series processors.