The performance demanded by smartphones and tablets is increasing at a much faster rate than the capacity of batteries or the semiconductor process node power savings. At the same time, users are demanding longer battery life within roughly the same form factor. This conflicting set of demands requires innovations in mobile SoC design beyond what process technology and traditional power management techniques can deliver. big.LITTLE is one of many power management technologies employed to save power in mobile SoCs – it works in tandem with Dynamic Voltage and Frequency Scaling (DVFS), clock gating, core power gating, retention modes, and thermal management to deliver a full set of power control for the SoC.
big.LITTLE technology takes advantage of the fact that the usage pattern for smartphones and tablets is dynamic: Periods of high processing intensity tasks, such as initial web page rendering and game physics calculation, alternate with typically longer periods of low processing intensity tasks such as scrolling or reading a web page, waiting for user input in a game, and lighter weight tasks like texting, e-mail and audio. The graph below shows the CPU utilization at various power states in a big.LITTLE SoC, with all the relevant power management techniques in operation. It clearly shows the usage of the big CPU cores in burst mode, or for short duration at peak frequency, while the majority of runtime is managed by LITTLE cores at moderate operating frequencies.
Innovative power savings techniques are required to sustain the pace of innovation in mobile through performance increases in the same power footprint. Many of the mobile use cases exhibit behavior like that shown in the graph above, presenting a very strong opportunity for big.LITTLE technology to save power while also delivering peak performance in modern mobile devices.
big.LITTLE Processing – How does it work?
The high performance and high efficiency CPU clusters are connected through a cache coherent interconnect fabric such as the ARM CoreLink™ CCI-400 . The processors look like one multicore CPU to the operating system. User space software on a big.LITTLE SoC is identical to the software that would run on a standard SMP processor. So how does the work get scheduled to the right processor?
ARM has developed a kernel space patch set gives the Operating System awareness of the big and LITTLE cores, and the ability to schedule individual threads of execution on the appropriate processor based on dynamic run-time behavior. The software also keeps track of load history for each thread that runs, and uses the history to anticipate the performance needs of a thread the next time it runs. This software is called Global Task Scheduling, and it is in operation on the use case graph above and in the measured results below, where big.LITTLE technology is delivering energy savings as high as 75% for the same or higher delivered performance.
The latest CPUs from ARM, including the ARMv8 architecture-based Cortex®-A53 and Cortex-A57 processors, fully support big.LITTLE and can be deployed using similar software. The processors are connected using the same CoreLink CCI-400 cache coherent interconnect in big.LITTLE SoCs. The Global Task Scheduling software is written to allow a migration to ARMv8 architecture support, with updated ARMv8 architecture patch sets coming in time for SoC launches with the Cortex-A50 series processors.