Low-Latency and High-Bandwidth Printf-Style Debug
The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time software instrumentation with no impact on system behavior or performance. It extends the low-cost real-time visibility of software and hardware execution to all software developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain. The STM-500 is for 64-bit systems and backward compatible to 32-bit.
Features and Benefits
The STM enables low-latency and high-bandwidth printf-style debug capability to give developers more visibility into their software. It does this without altering the system behavior, making it easier to develop and optimize software on Arm processor-based systems.
The CoreSight System Trace Macrocell is architected to provide the low-latency and high-bandwidth real-time system instrumentation required for real-time and application-based platforms. The Arm STM supersedes the Instrumentation Trace Macrocell (ITM) for these applications; for Cortex-M series processor-based devices, ITM remains the preferred solution.
The STM provides timing-accurate on-chip visibility of the software and hardware interaction. This enables Arm silicon partners and OEMs to optimize their SoCs even further and bring their platforms to market faster.
The CoreSight STM offers an industry standard across all markets for system visibility. All major tool vendors support Arm STM, which complements the industry-standard Embedded Trace Macrocell (ETM) and is compliant with MIPI System Trace specification.
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Talk with an Expert
System-level visibility is important during development. Find out how CoreSight STM helps reduce latency and increase throughput.
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Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.
- Technical Reference Manual
- CoreSight Technical Introduction
- CoreSight SoC enabling efficient design of custom debug and trace subsystems for complex SoCs
- Better Trace for better software with CoreSight STM
- Low Pin-count Debug Interfaces for Multi-device Systems
- Taking the fear out of silicon debug
- Video interview with CoreSight tech lead Mark LaVine