Pushing Compute to the Physical Extremes

Portrait of James Myers

James Myers, Distinguished Engineer and Devices, Circuits and Systems Research Lead

We believe in expanding the limits of ‘possible.’ Why should compute be limited to existing materials, methods, or design protocols? Our team explores and develops novel circuits and devices, enabling new applications where traditional systems may not be appropriate. We are investigating new materials in a landscape where silicon is no longer the only feasible option, enhancing system capabilities and redefining state-of-the-art performance.


The past year may have put a pause on a lot of usual activities, but amongst the new challenges and ways of working, our team have achieved some impressive feats.


M0n0 Diagram

A M0N0-based system


We’ve been actively working in the constrained world of ultra-low energy devices for some time. As part of DARPA’s N-ZERO program, we developed the first prototype ultra-low power Arm MCU, bringing the long-term deployment of devices and sensors in remote and inaccessible locations a significant step closer to reality. This project demonstrated an Arm Cortex-M33™ SoC with DSP and SIMD extensions, running on just 10µW active power, with single battery cell operation (1V – 1.5V) at 20µW/MHz.

Explore M0N0

 Even with ultra-low power operation, battery-based devices still have their limitations, which is why we’re taking our research a step further with Project Triffid. This project investigates whether it’s feasible to remove the battery altogether and enable billions of battery-less Arm devices.

Ultra-low power is one key challenge, but ultra-low cost has the potential to be equally valuable. In work featured on the front cover of Nature Electronics, we demonstrated how intelligence can be added to millions of everyday items, without the cost-prohibitive limitations of silicon design and manufacture. By implementing machine learning on a flexible substrate, we showed how data picked up by an e-nose sensor could be processed and decisions made based on the data, a task which could have valuable application, for example, in food packaging, reducing waste and increasing recycling potential.

And of course, we can’t neglect demand for continued performance improvement, as traditional scaling gains grind to a halt. Alternative designs such as 3D ICs show significant promise, but they are not without their challenges, one of which is the need to link design and test methodologies more effectively. Our 3D test vehicle, presented at IEDM 2020, is an essential step toward proving the viability of 3D designs for next-generation high-performance, energy-efficient ICs. Based on high-density, face-to-face wafer bonding technology, the test vehicle has 5.76µm-pitch 3D connections and 12nm FinFET devices, with a cache-coherent interconnect mesh. It operates at up to 2.4GHz, with 10x lower bandwidth density (3.4 TB/s/mm2) and energy usage (0.02 pJ/bit) than current state-of-the-art 2.5D/3D bump-based technologies.

Operating at the very extremes of compute means there are always challenges that require novel and creative thinking to overcome, but that’s what makes our work exciting. We’re looking forward to pushing those extremes out even further through 2021 and beyond as we still haven’t yet reached the limits of ‘possible.’