Market-Optimized 3nm Physical IP for Armv9-based CPUs
By Kiran Burli, senior director of marketing, Physical Design Group, Arm
For many decades, the computing industry has been focused on keeping pace with Moore’s Law by packing more compute into smaller areas. As Moore’s Law comes to an end, and new compute applications emerge, specialized processing will be the key to achieving the increased performance, power, and area (PPA) expected across the industry. The recently announced Armv9-A architecture will form the leading-edge of the next 300 billion Arm-based chips.
Arm partners are executing on plans for the future of computing today, and already leveraging the secure, powerful processing features of the new Armv9-A architecture to bring their innovations to life in next-generation SoCs. Market segments like premium mobile and hyperscale-cloud that require higher performance and power efficiency to process complex AI-based workloads are at the forefront of this development, and we are enabling their design with optimized physical IP and implementations, Arm POP IP, in TSMC 3nm technology.
Recently, a lead Arm partner successfully taped-out a test chip, validating Armv9 physical IP on TSMC 3nm process technology. It is exciting to see the Arm ecosystem take advantage of what Armv9 brings to the next decade of computing.
“We're pleased with the result of collaboration with Arm in delivering Arm cores with POP IP on TSMC's advanced process,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “This helps our mutual customers achieve silicon innovations benefitting from the significant power and performance boost of our 3nm technology and quickly launch their new product innovations to market.”
Armv9 SoCs are expected to have multiple CPU cores with complex interconnect and power management strategies, implementing standards such as AMBA CHI. This complexity inherently comes with challenges that need to be well understood for optimal implementation in 3nm technology. The goal is to optimize the "real" critical paths. Custom recipes and tight collaboration with electronic design automation (EDA) vendors improves the timing correlation between placement and final routing. Ultimately, there is a trade-off between hitting the target performance, managing power, and electromigration with a robust power grid. Logic and power grid optimization are essential for minimal voltage droop, timing, and routing congestion.
What stands out about Arm physical IP is it’s designed for high and low voltage tolerance, logic libraries with high-drive cells, technology files supporting aggressive via pillars or ladders, as well as high sigma timing sign-off using LVF – all of which are included in POP IP implementations for Armv9 Cortex and Neoverse cores.
To enable our partners to keep up with the rapid pace of computing innovation, we must ensure developers do not have to worry about the challenges that come with designing on a leading-edge technology node using a new core. The 3nm Armv9 POP IPs and the underlying Arm Artisan Physical IP are developed in close collaboration with the Arm processor development teams in an iterative process that identifies optimal performance and energy efficiency. The reality of the benefits of this physical IP can be seen in this example from our partner SiPearl who implemented POP IP for Neoverse to gain nearly ten years of development and help fine-tune its first generation of microprocessors for supercomputing.
The next decade will not only bring computing into new markets and applications, but will also bring a set of unique challenges and Armv9 is the foundation of leading-edge compute that will be ready to address those challenges. We are eager to see what the Arm ecosystem brings to life on leading-edge nodes like TSMC N3. Arm has early 3nm logic library and memory evaluation kits available to developers now, and you can contact us to hear more about our work on leading-edge nodes.
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