These new physical IP implementation solutions strengthen the commitment from ARM to enable delivery of real silicon with the speed consumers are demanding. Artisan Power Grid Architect creates power-optimized networks and removes the need for implementation teams to apply detailed FinFET design rules, allowing extra time to explore power network options for a particular design. Additionally, Artisan Power Grid Architect automates critical aspects of floorplanning to improve overall power, performance and area (PPA), especially for power grid design. Artisan Signoff Architect adds enhancements and more precision to stage-based on-chip variation (SB-OCV) signoff methodologies, adding accuracy that is not supported in the existing IP model format.
"ARM Physical IP for TSMC 16nmFinFET process technology ensures the availability of leading-edge design solutions for ARM-based SoCs," said Ron Moore, vice president of marketing, physical design group, ARM. "Artisan Power Grid Architect and Artisan Signoff Architect help to improve power, performance and area and provide a new level of signoff accuracy and reduced time-to-market for TSMC's FinFET process. These new implementation solutions underscore our commitment to innovation for our silicon partners."
Artisan Power Grid Architect and Artisan Signoff Architect are used exclusively with ARM Artisan advanced physical IP for TSMC 16nm FinFET (CLN16FF+). The beta release of Artisan Power Grid Architect for TSMC CLN16FF+ will be available October 2014, while Artisan Signoff Architect will be available for TSMC CLN16FF+ beta release in Q4 2014.
Head of technical PR, ARM
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