"Growth in mobile computing and the Internet of Things is connecting more devices and aggregating more data across the network, and that demands an increasingly flexible and efficient computing infrastructure," said James McNiven, general manager, systems and software group, ARM. "Our new CoreLink CCN-502 and CoreLink CCN-512 interconnects build on a common architecture, scaling from high efficiency Power-over-Ethernet wireless access points, to high compute density 48-core solutions."
Next generation infrastructure deployments require complex heterogeneous compute solutions that can address the demands of exponentially growing throughput demands without compromising on manageability and flexibility. The entire family of CoreLink CCN interconnects, including the CoreLink CCN-504 and CoreLink CCN-508, offer enterprise-class features such as RAS, ECC and advanced QoS to address a wide range of infrastructure SoCs ranging from 1 to 48-cores of CPU that can be coupled with a variety of heterogeneous compute elements. All CoreLink CCN interconnects include native ARM AMBA® 5 CHI interfaces providing high frequency, non-blocking data transfers and an integrated Level 3 Cache and Snoop Filter.
Optimized for area and power in Small Cell Base Stations and Wireless Access Points
CoreLink CCN-502 is an area-optimized interconnect for up to four quad-core processor clusters, offering the most cost and power-efficient solution in the CoreLink CCN family. Applications may include small cell base stations and sub-10W Power-over-Ethernet wireless access points.
Key benefits and features of the CoreLink CCN-502 include:
Highest Compute Density for Macro Cell Base Stations, Core Networks and Servers
The CoreLink CCN-512 is the highest performance solution in the CoreLink CCN family and offers partners the ability to create dense, 48-core heterogeneous compute solutions with a mix of CPUs, DSPs and accelerators and bandwidths up to 1.8 terabits per second.
Key benefits and features of the CoreLink CCN-512 include:
To-date, ARM has licensed the enterprise-class CCN CoreLink technology to more than ten silicon partners including AMD, Avago and Freescale. In addition there is wide ecosystem support for AMBA 5 CHI including verification IP from Cadence, Mentor and Synopsys.
"In order to deliver high-bandwidth and scalable cache coherent interconnect across our ARM Cortex-A57 based SoCs, AMD is pleased to announce that we have licensed and integrated ARM CoreLink CCN interconnects into our upcoming AMD Opteron™ A-Series SoC, codenamed 'Seattle' and the AMD Embedded R-Series SoC, codenamed 'Hierofalcon,'" said Suresh Gopalakrishnan, corporate vice president and general manager, server business unit, AMD.
"As SoC designs continue to grow in size and complexity, functional verification becomes an increasingly critical component of the development cycle," said Erik Panu, vice president, research and development, IP Group, Cadence. "The Cadence Verification IP solution for AMBA 5 CHI and JasperGold Intelligent Proof Kit for AMBA 5 CHI protocols are already helping ARM partners roll-out their next-generation designs incorporating the most advanced interconnect standards while speeding time to market."
"For ARM-based multi-core cache-coherent designs, Mentor delivers a competitive advantage with a solution that goes beyond traditional interconnect verification offerings," said John Lenyo, vice president and general manager, design verification technology division, Mentor Graphics. "The Questa® platform combines dynamic simulation and system-level verification IP to fully verify and analyze cache-coherent interconnect subsystem connectivity, functionality, and performance. The Veloce® platform then lets engineers scale their environments and verify their coherent interconnect subsystems within the context of an entire system, including software."
"Building on more than 20 years of close ARM and Synopsys R&D collaboration to deliver verification solutions, we are pleased to announce the production availability of Synopsys’ next-generation Verification IP (VIP) for the ARM AMBA 5 CHI interface specification," said Debashis Chowdhury, vice president of research and development, verification group, Synopsys. "The Synopsys VIP for AMBA 5 CHI is a complete, self-contained, 100% native SystemVerilog, UVM-based source-code test suite. It provides SoC teams, including those using the new ARM CoreLink CCN-502 and CCN-512 interconnect, with the built-in protocol knowledge, features and methodology they need to increase design quality. As part of the Verification Compiler product, this VIP - through its native integration with simulation, debug, and coverage - provides a significant performance and productivity benefit, further accelerating time-to-market."
Head of technical PR, ARM
ARM is at the heart of the world's most advanced digital products. Our technology enables the creation of new markets and transformation of industries and society. We design scalable, energy efficient-processors and related technologies to deliver the intelligence in applications ranging from sensors to servers, including smartphones, tablets, enterprise infrastructure and the Internet of Things.
Our innovative technology is licensed by ARM Partners who have shipped more than 60 billion System on Chip (SoCs) containing our intellectual property since the company began in 1990. Together with our Connected Community, we are breaking down barriers to innovation for developers, designers and engineers, ensuring a fast, reliable route to market for leading electronics companies. Learn more and join the conversation at http://community.arm.com.
AMBA, ARM, CoreLink and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other brands or product names are the property of their respective holders. "ARM" refers to ARM Holdings plc (LSE: ARM and NASDAQ: ARMH) and members of its corporate group as constituted from time to time.
None of the information contained in this document may be adapted, republished, or reproduced in any form except with the prior written permission of the copyright holder, but links may be posted directly to this document from other websites, and the whole of the document correctly attributed and unmodified may be shared freely, unless the copyright holder at any time withdraws these permissions. This document is intended only to provide information to the reader about the relevant product(s) described or mentioned. All information is provided "as is" and without warranty. ARM makes no representation as to the product(s), and ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information.