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CoreLink CCN-504 cache 一致性网络

The ARM® CoreLink CCN-504 Cache Coherent Network is optimised for mid-range systems with up to 16 processor cores. This give system architects an optimal solution for enterprise applications including servers and network infrastructure.

CoreLink CCN-504 includes an integrated Level 3 Cache from 1 to 16MB, which places it in the middle of the range of the ARM CCN series. The CoreLink CCN-504 offers high bandwidth interconnect supporting AMBA 5 CHI protocol and bandwidth approaching 1 terabits per second.

CoreLink CCN-504 is optimised for the latest ARMv8 64-bit processors including Cortex-A57 and Cortex-A53. CoreLink CCN-504 is part of a series of products offering designers a scalable, cache coherent interconnect for 'many core' networking infrastructure and sever solutions.

Optimized for Small to Mid-Range Infrastructure

  • CoreLink CCN-504 is designed for small area, power optimized network infrastructure and server applications.
  • High frequency, high performance cache coherent interconnect supporting up to 1 Tbps sustained banwidth.
  • Example applications - small enterprise solutions, cellular small cell, media content.

Optimized for ARM Cortex Processors

The CoreLink CCN-504 supports the high efficiency Cortex-A15 processor and the latest Cortex-A53 and Cortex-A57 processors, and is in the series of ARM CoreLink CCN that support the AMBA® 5 CHI. This new coherent hub interface has been developed to support high frequency, non-blocking data transfers between multiple fully coherent processors.

Integrated Low Latency Level 3 Cache

The CoreLink CCN-504 Cache Coherent Network includes integrated level 3 (L3) cache and snoop filter functions. The L3 cache, which is configurable up to 16MB, extends on-chip caching for demanding workloads and offers low latency on-chip memory for allocation and sharing of data between processors, high-speed IO interfaces and accelerators. The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.

High Performance DDR3 and DDR4 Memory Interfaces

The CoreLink CCN-504 is optimized to work with the CoreLink DMC-520 Dynamic Memory Controller providing high-bandwidth interface for off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. CoreLink DMC-520 offers enterprise class RAS (Reliability, Availability and Serviceability) features such as ECC for x72 DRAM, TrustZone security and end-to-end QoS.




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