AHB interfaces are also supported in the CoreLink Network Interconnect (NIC-400).
For Cortex-M family designs please also see the Cortex-M System Design Kit that is further optimized for these processors and includes example system designs.
The configurable AHB Bus Matrix allows the designer to create an optimized multi-layer AHB interconnect. The independent AHB layers allow simultaneous transfers between different masters and slaves, which increases system performance. The Bus Matrix includes address decoding per master, and arbitration at each slave. The arbitration is configurable for round robin or priority encoding. A simple Perl script, or from the AMBA Designer tool drives the configuration and generation of the AHB Bus Matrix.
The File Reader Bus Master is a powerful AHB verification component that can drive any bus transfer under the command of a text file. This is useful to test system integration, for example, to verify the memory map of a system by reading and writing to peripheral registers.The full list of components in the AMBA Design Kit:
- Configurable Multi-layer AHB Interconnect
- File Reader Bus master for verification
- Static memory Controller
- Interrupt Controller
- Remap and Pause Controller
- Watchdog timer
- Reset Controller
- General Purpose IO (GPIO)
- Example AMBA System (EASY)
- Example Re-try Slave
- Example Bus Master
- Example APB Slave
- AHB Synchronous Bridge
- AHB Asynchronous Bridge
- AHB Synchronous-up Bridge
- AHB Synchronous-down Bridge
- AHB Pass-through Bridge
- AHB-to-APB Bridge
- AHB Downsizer
- Tube verification component for simulation printf
- TIC Box
For designs using AMBA 3 AXI you should use the CoreLink NIC-400 Network Interconnect.
For Cortex-M family AHB designs you should use Cortex-M System Design Kit.