CoreSight SoC

CoreSight  SoC-400 is the comprehensive solution for debug & trace system design.  Until now CoreSight components have always been provided as part of a processor-specific design kit.  Design kits include a simple example of a debug & trace system for a single core system.  CoreSight SoC-400 provides fully configurable versions of all of the CoreSight components together with AMBA Designer support for the entire range of CoreSight debug & trace logic.

CoreSight Soc-400 enables quick and easy creation of complex custom debug and trace systems  IP stitching and test-bench generation. 

Appropriate integration libraries provide support for all ARM processors in CoreSight SoC-400. The integration library ensures that the CPU and trace macrocell signals are CoreSight SoC ready.

CoreSight SoC-400 is a debug subsystem design and validation flow aimed at reducing risk, accelerating and optimizing debug implementation in heterogeneous and multi-core SoCs. It provides a kit of parts that you can use to build and validate debug and trace elements of a System-on-Chipallowing you to create bespoke debug solutions for complex multi-processor SoCs. The table below describes what is included in SoC-400 r3p1 product.

SoC-400 Component


Library of configurable components + configuration scripts

Verilog components to implement CoreSight functionality for debug, trace, cross-triggering and timestamps. Comes with scripts to render configured instances of the components based on the user requirements.

Optional GUI flow

IP-XACT component views allow the user to graphically configure, integrate and stitch the components and ARM processors.  ARMs AMBADesigner or other IP-XACT compatible stitching tools can be used.

Support for System Trace Macrocell (STM) & Trace Memory Controller (TMC) and Embedded Trace Macrocells (ETM)

These separately licensed components are supported within the SoC-400 flow of configuring and stitching components.

Support for processor debug integration

 The most recently released processors natively support CoreSight SoC. Integration of older processors with CoreSight SoC is implemented using Processor Integration Layers (PILs), a wrapper layer that provides the required debug integration capability.


SoC-400 consolidates the CoreSight component documentation for the latest generation of IP. It consists of a Technical Reference Manual, User Guide, Implementation Guide, CoreSight Architecture Specification, System Design Guide and Integration Manual to help with your SoC design.

Validation Components

Verification IP, C-language test cases, worked example designs and testbenches

Table 2: SoC-400 components

SoC-400 is used alongside ARM CPU products and advanced debug and trace components, such as the STM and TMC, to build a comprehensive and custom SoC debug and trace solution.


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