ARM® CoreSight™ SoC-400 is the comprehensive debug & trace solution for system design. Until now CoreSight components have always been provided as part of a processor-specific design kit. Design kits include a simple example of a debug & trace system for a single core system. CoreSight SoC-400 provides fully configurable versions of all of the CoreSight components together with CoreSight Creator support for the entire range of CoreSight debug & trace logic.
CoreSight SoC-400 enables quick and easy creation of complex custom debug and trace System IP stitching and test-bench generation.
The current trend in the electronics industry is towards increasingly complex hardware with ever-rising software development costs with much-reduced time-to-market. Original Equipment Manufacturers (OEMs) are expecting silicon providers to give a reliable and complete hardware and software system ready for applications development, and this is a key differentiator.
A well thought-out debug and trace solution helps silicon providers address these challenges.
Introduction to ARM CoreSight SoC-400
ARM CoreSight debug and trace technology offers a comprehensive solution for the entire SoC. CoreSight SoC-400 is a kit of parts that enables software developers and SoC designers to develop high-performance systems while decreasing development time and risks.
Comprehensive debug & trace solution
CoreSight SoC-400 is a debug subsystem design and validation flow aimed at reducing risk, accelerating and optimizing debug implementation in heterogeneous and multi-core SoCs. It provides a kit of parts that you can use to build and validate debug and trace elements of a System-on-Chip allowing you to create bespoke debug solutions for complex multi-processor SoCs. CoreSight SoC-400 is used alongside ARM CPU products and advanced debug and trace components, such as the STM and TMC, to build a comprehensive and custom SoC debug and trace solution.
Faster bring up means a reduced time-to-market
Hardware/Software co-development via debugger in simulation and emulation
Performance optimization (both hardware and software)
Reduced bug cost
Reduced time to market
"ARM CoreSight debug and trace technology was instrumental to the successful bring-up of the Exynos 7870. When designers are working on optimizations to eke out the maximum performance, there is peace of mind in knowing that CoreSight gives the best real-time trace delivering visibility onto the chip fast in order to fine tune the performance" Samsung Exynos 7870
"In addition, ARM CoreSight debug and trace technology was implemented in the chip’s development to provide on-chip visibility that enables fast diagnosis of bugs and performance analysis. Amongst other things, CoreSight ensures it meets the high quality standards required by ISO 26262." Xilinx Zynq-7000
Key steps to create a debug and trace solution for an ARM SoC
The global cost of debugging software has risen to $312 billion annually. A new whitepaper: "CoreSight SoC enabling efficient design of custom debug and trace subsystems for complex SoCs", outlines the key steps to create a debug and trace solution for an ARM SoC.
Technical Introduction to ARM CoreSight
ARM® CoreSight™ technology is the industry name for debug and trace. This document introduces the concepts which will help you to get the most out of CoreSight. You will learn:
- Elements of a CoreSight design
- Processor trace architectures
- Debug access and DAP topology
- Typical CoreSight systems
Better trace for better software with ARM CoreSight
This white paper explores the limitations of existing software debug and trace technologies, and explains how the ARM® CoreSight™ System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, whilst leveraging existing open source trace infrastructures.
Low Pin-count Debug Interfaces for Multi-device Systems
This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, whilst maintaining support for multi-core systems and interoperability with test.