Cortex-A12 Processor

Cortex-A12 Processor Image (View Larger Cortex-A12 Processor Image)
The ARM® Cortex®-A12 processor is the highest performance mid-range mobile processing solution designed for mobile applications like the use in smartphones and tablets devices. The Cortex-A12 processor is the successor to the highly successful Cortex-A9 processor and is optimized for highest performance in the mainstream mobile power envelope leading to best-in-class efficiency.

The Cortex-A12 processor, and its high performance and high-end feature set, unlocks many new use cases available exclusively in Premium devices today. Mid-range devices can finally build on the success of high-end devices and continue driving the fastest growing market segment in mobile. Features include, but not limited to:

  • 1TB addressable memory space – supporting future needs of mobile software
  • Virtualization and TrustZone® security technology – security enabling new use cases like BYOD for your mobile device

Supported by a range of other ARM technology IP including ARM System IP, ARM POP IP and development tools, the Cortex-A12 processor enables ARM powered solutions that contribute to the very best user experience in terms of responsiveness and battery life. The Cortex-A12 processor is a highly tuned processor that will bring the performance of high-end mobile devices into mid-range smartphone and tablets, as well as into other great consumer market opportunities.



The Cortex-A12 processor is bringing high performance into the mid-range and its efficiency profile makes it an ideal choice for thermally restricted mobile devices like smartphones and tablets.

The Cortex-A12 processor is based on the widely adopted ARMv7-A architecture and offers backwards compatibility to the Cortex-A15, Cortex-A7 and Cortex-A9 processors and allows existing applications to operate seamlessly on Cortex-A12 processor-based SoCs. The Cortex-A12 is an attractive next step for the Cortex-A9 designs in the market place today as a standalone solution. Future variants will be big.LITTLE compatible and allow big.LITTLE configuration with the high-efficiency Cortex-A7 processor.

The Cortex-A12 microarchitecture consists of a high-performance, high-efficiency pipeline, which delivers significant performance increase over today’s mid-range devices while maintaining uncompromised battery life expected in this market. Tightly integrated NEON™/FPU units, integrated L2 cache with optional reliability features, peripheral port for low-latency peripheral accesses and an Accelerator Coherency Port (ACP) are just some features available in the Cortex-A12 processor making it an ideal choice for the mid-range mobile market, and other consumer centric applications.


The Cortex-A12 processor is designed for mobile, but fits into many other use-cases, for example:

  • Smartphones, Tablets
  • Digital TV
  • Home Networking
  • Other consumer applications

The Cortex-A12 processor is a successor to the Cortex-A9 processor and increases its performance by 40% and matches the best-in-class energy efficiency

The Cortex-A12 processor brings today’s premium smartphone features into the midrange. This includes hardware support for OS virtualization and support for addressing upto 1TeraByte of physical memory.

Initially used for high-end solutions leveraging the Cortex-A7 and Cortex-A15 processors, as well as for ARMv8 products like the Cortex-A57 and Cortex-A53 processors, big.LITTLE has been an innovative technology for increasing performance and efficiency. big.LITTLE will migrate to midrange SoCs and allow devices to increase the dynamic range beyond what standalone solutions can achieve.

Cortex-A12 Processor
Architecture ARMv7-A Cortex
Multicore 1-4X SMP within a single processor cluster
Multiple coherent processor clusters through AMBA® 4 technology
ISA Support ARM
TrustZone® security technology
NEON™ Advanced SIMD
DSP & SIMD extensions
VFPv4 Floating point
Hardware virtualization support
Large Physical Address Extensions (LPAE)
Memory Management ARMv7 Memory Management Unit
Debug and Trace CoreSight™ SoC-400
Cortex-A12 Processor Key Features
Thumb-2 Technology Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions
TrustZone Technology Ensures reliable implementation of security applications ranging from digital rights management to electronic payment
NEON NEON technology can accelerate multimedia and signal processing algorithms such as video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis
DSP & SIMD Extensions Increase the DSP processing capability of ARM solutions in high-performance applications, while offering the low power consumption required by portable, battery-powered devices. The DSP extensions are optimized for a broad range of software applications including servo motor control, Voice over IP (VOIP) and video & audio codecs.
Floating-Point Hardware support for floating-point operations in half-, single- and double-precision floating point arithmetic. The floating-point capabilities of the Cortex-A12 processor offer increased performance for floating point arithmetic used in next generation mobile devices
Hardware Virtualization Highly efficient hardware support for data management and arbitration, whereby multiple software environments and their applications are able to access simultaneously the system capabilities. This enables the realization of devices that are robust, with virtual environments that are well isolated from each other.
Large Physical Address Extensions (LPAE) The introduction of Large Physical Address Extensions (LPAE) enables the processor to access up to 1TB of memory.
Optimized Level 1 Caches Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. Caches are configurable size 32kB – 64kB for instruction, and 32kB for data. Also providing the option for cache coherence for enhanced inter-processor communication or support of rich SMP capable OS for simplified multicore software development
Integrated, Configurable Size Level 2 Cache Controller Providing low latency and high bandwidth access to up to 8 MB of cached memory in high frequency designs, or design needing to reduce the power consumption associated with off chip memory access.
Peripheral Port This AMBA® 4 AXI™ compatible master interface allows for low-latency accesses to peripherals effectively eliminating any traffic congestion between transactions going to peripherals and main memory resulting in higher overall performance.
Accelerator Coherency Port (ACP) This AMBA® 4 AXI™ compatible slave interface allows an external master to participate in the cache coherency mechanism of the Cortex-A12 processor which reduces the overhead of performing coherency maintenance in software.

The Cortex-A12 processor is supported by a complete ARM IP product portfolio, including:
  • ARM POP™ IP for various advanced nodes for optimized implementations reducing risk and shortening time-to market
  • Enhanced ARM Mali™ Graphics and Video IP including the Mali-T622 and Mali-V500 solutions
  • ARM Systems IP allowing a rapid system design
  • Broad range of development tools including the ARM DS-5™ toolchain

ARM has designed the Cortex-A12 processor to work efficiently with a complimentary family of high performance, low power ARM CoreLink™ System IP components. ARM supplies all the major components to move and store data between processors and memory. This includes the CCI-400 cache coherent interconnect, NIC-400 network interconnect, DMC-400 dynamic memory controller and MMU-400 system memory management unit as well as fully featured cache controllers, DMA controllers, static memory controllers and memory interface PHYs to the highest specifications. AMBA design tools enable the easy configuration, performance exploration and verification of the ARM subsystem.

Cortex-A12 Companion IP
AMBA 4 Cache Coherent Interconnect (CCI-400)
  • The CCI-400 provides AMBA® 4 AXI™ Coherency Extensions (ACE) compliant ports for full coherency for The Cortex-A12 processor and other Cortex processors, better utilizing caches and simplifying software development. This feature is essential for high bandwidth applications including future mobile SoCs that require clusters of coherent processors or GPUs. Combined with other available ARM CoreLink™ System IP, the CCI-400 increases system performance and power efficiency.
  • CoreLink CCI-400 Cache Coherent Interconnect provides system coherency with Cortex processors and an IO Coherent channel with Mali IP and opens up a number of possibilities for offload and acceleration of tasks. When combined with a Cortex-A7 processor, CCI-400 allows big.LITTLE operation with full L2 cache coherency between the Cortex-A12 and Cortex-A7 processors.
Efficient voltage scaling and power management is enabled with the CoreLink ADB-400 unlocking DVFS control of the Cortex-A12 processor. Further 'extension' of the DVFS curve also comes when used with the Cortex-A7 processor.
AMBA Generic Interrupt Controller (GIC-400) AMBA Interrupt Controllers like the GIC-400 provide an efficient implementation of the ARM Generic Interrupt Specification to work in multi-processor systems. They are highly configurable to provide the ultimate flexibility in handling a wide range of interrupt sources that can control a single CPU or multiple CPUs.
AMBA 4 CoreLink MMU-500 CoreLink MMU-500 provides a, hardware accelerated, common memory view for all SoC components and minimizes software overhead for virtual machines to get on with other system management functions.
CoreLink TZC-400 The Cortex-A12 processor also enjoys a secure, optimized path to memory to further enhance its market leading performance with the aid of CoreLink TZC-400 TrustZone® address space controller
CoreLink DMC-400 All interconnect components and the ARM DMC guarantee bandwidth and latency requirements by utilizing in-built dynamic QoS mechanisms.
CoreSight™ SoC-400 ARM CoreSight™ SoC debug and trace hardware is used to profile and optimize the system software running through-out from driver to OS level.


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