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Latest blog posts

December 2, 2025

Reading time 3 minutes

Halide: A novel programming paradigm for advanced image processing

Éliás Bálint

November 28, 2025

Reading time 11 minutes

Rethinking the role of CPUs in AI: A practical RAG implementation on DGX Spark

odinlmshen

November 28, 2025

Reading time 4 minutes

Rethinking Gen Z and the future of the semiconductor workforce

Rachael Horsman

November 12, 2025

Reading time 3 minutes

AI Chat: Explore and evaluate LLMs on Android and ChromeOS

Han Yin

Latest community activity

Today

Toshihisa Oishi

replied to this:

Gal Kaptsenelasked a question in

Support forumsSoC Design and Simulation forum

3 days ago

Fast Models For Academic research

Hello,

I am a researcher at the Technion working on Revizor (https://microsoft.github.io/sca-fuzzer).

For my research, I need a microarchitectural branch predictor simulator for AArch64.

Ideally, I am looking for an accurate microarchitectural simulation...

Toshihisa Oishiabout 3 hours ago

Hi Gal Kaptsenel,

Fast Models won't suite your use case because Fast Models are not designed to be cycle accurate e.g. RISC pipelining is not modelled. Please check the link below to know what FM can do and cannot do:

https://developer.arm.com/documentation/100964/1130/About-the-models/Model-capabilities

Thanks,
Toshi

December 3, 2025

Haroon Ahmed

earned the Ask A Question I achievement.

Ask a question in a forum.

Haroon Ahmedasked a question in

Support forumsSoC Design and Simulation forum

about 11 hours ago

AHB: Address and control signal stable during waited write access

Hi,

During the waited states of write access (data-phase of write access), address and control signal should be stable (include HWRITE) until HREADYOUT is high. Why the master needs to keep the address and control signals stable during the waited states...

Nakhyeon Kimasked a question in

Support forumsArchitectures and Processors forum

1 day ago

AFREADY reset value of ATB master I/F in CSTFunnel is 1'b0

Regarding to ATB spec (ARM IHI 0032C (ID120321)) captured as below,

When ATB master can not respond(e.g. CLK gating), it must assert AFREADY as High.

I think If AFREADY is made by a register, Its reset value must be 1'b1(High).

But AFREADY reset...

Chiranmoy Bhattacharya

replied to this:

Chiranmoy Bhattacharyaasked a question in

Support forumsHigh Performance Computing (HPC) forum

3 months ago

Exploring Opportunities to Speed Up Vector API Performance on Arm

Hi HPC Community,

We have recently used the Vector API to implement bit packing and unpacking of boolean values.

For benchmarking, we've used JMH with JDK 24

Bit-packing: We used VectorMask.fromArray(…).toLong(…)and observed some speed...

Mikhail Ablakatov3 months ago

Hi Chiranmoy,

Thanks for the report. We're planning to reproduce this on the JDK mainline and we'll share findings as we learn more.

If you could share the benchmark you've used or another minimal reproducer test case, that would help.

Chiranmoy Bhattacharyain reply to Mikhail Ablakatov1 day ago

Hi Mikhail,

The issue got resolved after the PR https://github.com/openjdk/jdk/pull/27481 was merged recently. The benchmark performance is now acceptable.

I'll be closing the discussion.

Thank you for the support.