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The SoC Design community is dedicated to design engineers developing highly integrated system-on-chip solutions with ARM technology. This site addresses every phase of SoC design, from architecture selection through front end design and back end implementation and manufacturing. Learn more about best practices for designing advanced SoCs based on ARM Cortex processors, Artisan physical IP, CoreLink system IP and ARM Connected Community IP, tools and services.

Industry Insight
Core Pattern Conversion for SoC Test: Beware of the "Poison Perl"

May 23 2012, 07:40 AM
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Bringing test patterns for your ARM core or other core-level blocks together for chip-level test of your SoC can present significant challenges. Whether your core-level test patterns are scan-based or functional, eventually they will likely end up in IEEE 1450 STIL format. At this point you may opt to make some modifications to these ASCII STIL files with Perl scripts or similar to prepare them for chip-level application. The scripts may seem simple at first—maybe you simply rename signals for chip-level access. But soon your requirements ex...

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