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ARM And Cadence Enable ARM Core-Based Designs Through The Silicon Design Chain

24 September 2003

New Signal Integrity-Enabled Reference Methodology Offers Rapid and Predictable ARM Soft IP Implementation

 

SAN JOSE, Calif., AND CAMBRIDGE, UK – Sept. 17, 2003 –Cadence Design Systems Inc., (NYSE:CDN), and ARM [(LSE: ARM); (Nasdaq: ARMHY)], the industry's leading provider of 16/32-bit embedded RISC processor solutions, today announced the availability of the ARM-Cadence Reference Methodology, based on the Cadence® Encounter™ digital IC design platform. Included in the ARM-Cadence Reference Methodology is support for the signal integrity-enabled flow, which incorporates CeltIC™ crosstalk analysis and repair and VoltageStorm™ power grid analysis; core technologies of the Encounter platform.

The ARM-Cadence Reference Methodology is a shrink-wrapped reference flow that provides predictable RTL-to-GDSII implementation for ARM® Partners and enables predictable performance, power and area results. The methodology also provides the accurate abstract models required for SoC integration. The new ARM-Cadence Reference Methodology utilizes all of the Cadence Encounter platform technologies, including the newly acquired Verplex Conformal logic equivalence checker.

"This Reference Methodology represents a significant step for customers of ARM and Cadence in terms of methodology capability," said Noel Hurley, EDA Relations manager at ARM. "This new, jointly developed reference methodology gives our mutual customers the flexibility to utilize ARM soft IP whilst also reducing possible signal integrity failures, ensuring predictable performance and reducing the overall development time to silicon."

"The ability to implement ARM soft IP quickly and predictably is critical for the success of today's nanometer designs. The ARM-Cadence Reference Methodology enables the right mix of technology to tackle this new generation of design," said Jan Willis, vice president of strategic third-party programs at Cadence Design Systems. "The development of this reference flow is a result of our collaboration with ARM to optimize the silicon design chain for our customers."

Cadence Encounter platform technologies supported in the ARM-Cadence Reference Methodology include the SoC Encounter RTL-to-GDSII System (which includes BuildGates® Synthesis, Cadence Physically Knowledgeable Synthesis, NanoRoute™ Ultra Nanometer Router and CeltIC Crosstalk Analyzer), Fire & Ice QXC, Assura™ DRC, VoltageStorm Power Grid Verification and Verplex Conformal Logic Equivalence Checker.

The ARM-Cadence Reference Methodology benefits from the extensive experience that Cadence has in delivering nearly 40 successful tape-outs of ARM Powered® designs. Cadence was the first member of ATAP™, the ARM technology access program. In March of 2003, the two companies announced a five-year agreement targeting silicon design chain optimization. This agreement builds on the companies' existing cooperation on verification, verification acceleration/emulation and signal integrity.

Availability
The ARM-Cadence Reference Methodology will be available from ARM in Q4 2003 (Beta available now) and supports the ARM946E-S™ core initially. ARM-Cadence Reference Methodology support for all other ARM soft cores will be provided in the future.

About ARM
ARM is the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions. The company licenses its high-performance, low-cost, power-efficient RISC processors, peripherals, and system-chip designs to leading international electronics companies. ARM also provides comprehensive support required in developing a complete system. ARM's microprocessor cores are rapidly becoming a volume RISC standard in such markets as portable communications, hand-held computing, multi-media digital consumer and embedded solutions. More information on ARM is available at http://www.arm.com/

About Cadence
Cadence is the world's leader in electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,000 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.

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Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. Cadence BuildGates is a registered trademark of Cadence Design Systems, Inc. Cadence Encounter, CeltIC, NanoRoute and Assura are trademarks of Cadence Design Systems, Inc. All trademarks are the property of their respective owners.

ARM and ARM Powered are registered trademarks of ARM Limited. ARM946E-S and ATAP are trademarks of ARM Limited. "ARM" is used to represent ARM Holdings plc (LSE: ARM and Nasdaq: ARMHY); its operating company ARM Limited; and the regional subsidiaries ARM INC; ARM KK; ARM Korea Ltd; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; and ARM Belgium N.V.

 

For more information, please contact:
Judy Erkanat
Cadence Design Systems
408-897-2302
jerkanat@cadence.com

Karin Gilles
The Hoffman Agency
408-975-3038
kgilles@hoffman.com





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