Design Automation Conference (DAC)
Venue:
Moscone Center
Location:
747 Howard Street, San Francisco, CA 94103
Date:
03 June 2012 - 07 June 2012
Room/Booth/Stand:
The Design Automation Conference is the world's leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business. DAC is also where the latest technical research is presented. DAC covers all topics related to the design of complex systems on chip: Embedded System design down to physical layout verification. Now in its 49th consecutive year, DAC is the most respected name in the chip design community.
ARM along with several of our Connected Communtity™ partners will be demonstrating a variety of ARM IP based solutions and design strategies.
More information will be forthcoming
For additional event information please visit the DAC event page
Collaboration across the electronics industry is essential to drive greater industry innovation and ensure customer success. Learn how ARM and its Connected Community partners are working together with the world’s leading semiconductor and consumer electronics companies to bring innovative, energy-efficient and high-performance devices to market that are powering the world around us and enabling the “Internet of Things.”. Hear about the latest ARM solutions, as well as success stories of collaborative efforts from customers and partners.
Monday, June 4, 2012
| Time | Partner/Customer/ARM | Presentation Title | Presenter |
|---|---|---|---|
| 10:00AM | ARM | Building compute sub-systems Cortex processors with CoreLink 400 system IP | Paul Martin |
| 10:30AM | Mentor | Tessent Support of ARM Cores and Memories: Comprehensive and Integrated Test Solutions | |
| 11:00AM | EVE | Hardware/Software Co-verification with EVE and ARM | Lauro Rizzatti, GM and WW VP Marketing |
| 11:30AM | TSMC | ||
| 1:30PM | Vworks/ASTC | Powered by VLAB – A new generation of Virtual Development Platforms and Products | Jay Yantchev, CEO, ASTC / VWorks |
| 2:00PM | ARM | An ARM perspective on "what's next" in SoC power management | David Flynn |
| 2:30PM | Cadence | Delivering Low-Power Mixed-Signal Designs with an Embedded ARM Cortex-M Processor | Malden Nizic, Engineer Director |
| 3:00PM | Space Co-design | ESL Hardware/Software Codesign for ARM-based FPGA | Guy Bois, PresidentLaurent Moss, CTOGary Dare, General Manager |
| 3:30PM | ARM | Implementation of big.LITTLE | Dermot O'Driscoll |
| 4:00PM | Synopsys | ||
| 4:30PM | ARM | TBD | Rob Aitken |
| 5:00PM | Atrenta | Early PPA Analysis for AMBA-based Designs | Dr. Bernard Murphy, CTO, Atrenta |
| 5:30PM | Drawing for Apple® TV® |
Tuesday, June 5, 2012
| Time | Partner/Customer/ARM | Presentation Title | Presenter |
|---|---|---|---|
| 10:00AM | ARM | FinFET | David Pietromonaco |
| 10:30AM | Cadence | Enabling Faster and Lower Power ARM High-Performance Processors | James Davey, Marketing Director |
| 11:00AM | Apache | Power Budgeting with RTL Power Models for ARM IP-Based SoC Designs | Vic Kulkarni, Senior VP and GM, RTL Business Unit |
| 11:30AM | Samsung | ||
| 1:30PM | Jasper | Leveraging Formal Apps to Solve Tough Challenges and Improve Productivity Throughout the Design and Verification Flow | Oz Levia Vice President, Marketing |
| 2:00PM | ARM | Better memory | Betina Hold |
| 2:30PM | Synopsys | ||
| 3:00PM | Zocalo | Zocalo Tech: Debugging Assertions Prior to Being Launched in the Verification Flow | Robert Biczek, VP Worldwide Sales |
| 3:30PM | ARM | Getting your ideal debug and trace capabilities with the minimum of fuss | Barry Spotts |
| 4:00PM | Mentor | Mentor Graphics Transforms Verification of ARM-powered SoCs | Dennis Brophy, Director, Strategic Business Development |
| 4:30PM | ARM | An ARM perspective on "what's next" in SoC power management | David Flynn |
| 5:30PM | Drawing for Apple® TV® |
Wednesday, June 6, 2012
| Time | Partner/Customer/ARM | Presentation Title | Presenter |
|---|---|---|---|
| 10:00AM | ARM | Fast Models in SystemC/TLM design flows | Robert Kaye |
| 10:30AM | Synopsys | ||
| 11:00AM | Carbon Design Systems | Accelerating the Development and Optimization of ARM-based SoCs | Bill Neifert, CTO, Founder |
| 11:30AM | GLOBALFOUNDRIES | ||
| 1:30PM | ARM | 20nm | Paul de Dood |
| 2:00PM | Cadence | Cadence System-to-Silicon Solution for ARM processors | Frank Schirrmeister, Product Management Group Director, System Design and Verification |
| 2:30PM | ARM | Big.LITTLE System Architecture from ARM: Saving Power through Heterogeneous Multiprocessing and Task Context Migration | Brian Jeff |
| 3:00PM | SpringSoft | FPGA Prototyping - Debug and Verification with Protolink | Sam Miller |
| 3:30PM | ARM | FinFET | David Pietromonaco |
| 4:00PM | Mentor | Tessent Support of ARM Cores and Memories: Comprehensive and Integrated Test Solutions | Steve Pateras, Product Marketing Director, Silicon Test Products |
| 5:30PM | Drawing for Apple® TV® |
Conference Speakers
Hear from ARM executives, technology experts, and panelists as they discuss industry trends to help you prepare for the future and stay ahead of the competition.
| Date | Time | Location | Type | Topic | Speaker |
|---|---|---|---|---|---|
| Monday, June 4 | 8:30 AM — 5:30 PM | 309 | Tutorial | Pre-Silicon, Native Embedded Software Development Solutions | Robert Kaye, ARM |
| Tuesday, June 5 | 8:30 AM — 9:30 AM | 102/103 | Keynote | Scaling for 2020 Solutions | Mike Muller, CTO, ARM |
| Tuesday, June 5 | 1:30 PM — 3:00 PM | 305 | Panel | System Models – Does One Size Fit All? | John Goodenough, ARM |
| Tuesday, June 5 | 4:00 PM — 6:00 PM | 300 | Research Paper Session | Exploring Sub-20nm FinFET Design with Predictive Technology Models | Saurabh Sinha, ARM |
| Wednesday, June 6 | : 4:00 PM — 6:00 PM | 308 | Research Paper Session | A QoS-Aware Memory Controller for Dynamically Balancing GPU and CPU Bandwidth Use in an MPSoC | Chander Sudanthi, ARM |
| Thursday, June 7 | 1:30 PM — 3:00 PM | 310 | Special Session | big.LITTLE System Architecture from ARM: Saving Power through Heterogenous Multiprocessing and Task Context Migration | Brian Jeff, ARM |
| Thursday, June 7 | 3:30 PM — 5:30 PM | 300 | Research Paper Session | Yielding in an Uncertain World | Rob Aitken, ARM |
DAC will be held at the Moscone Convention Center in San Francisco, CA.
If you are in the San Jose area and need a worry-free and inexpensive way to get to the Moscone Center, consider taking the bus!
New this year, DAC is providing bus transportation from one location in the San Jose area to the South Lobby of the Moscone center. The buses will run Monday, June 4 - Wednesday, June 6. Parking at the bus pick-up location will be free. Pick-up and departure times are listed below.
The DAC bus program is the least expensive option compared to the Caltrain or BART. Tickets can be included in your conference or booth staff registration.
If you have already pre-registered, go to the link in your confirmation email to add it. If you have not yet registered, click on the tab titled BUS TRANSPORTATION TICKETS during registration before you checkout.
Location:
Cadence Design Systems, Inc.
Parking Lot
2655 Seely Avenue, San Jose, CA 95134
Pick-up times from San Jose to the Moscone Center (approximately 1 hour ride):
7:00AM, 7:30AM & 8:00AM
Departure times from the Moscone Center to San Jose
:6:45PM, 7:15PM & 7:30PM
Buses are tentatively scheduled at three times each morning and evening for your convenience. You will be able to choose your pick-up and departure times during registration. Your Confirmation Email will be required to ride the bus.
To learn more about San Francisco and find out more information about transportation and sites to see while you’re there, visit the DAC website: www.dac.com
