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Verification Methodology Manual for Low Power

Verification Methodology Manual for Low Power book coverby Srikanth Jadcherla (Synopsys, Inc.), Janick Bergeron (Synopsys, Inc.), Yoshio Inoue (Renesas Technology Corp) & David Flynn (ARM)

Available at no cost via electronic (PDF) download to current Synopsys customers. You will be asked for your SolvNet ID and password (if you don't have one already, it's easy to register).

Leveraging years of collective industry best practices, the Verification Methodology Manual for Low Power (VMM-LP) introduces a new verification methodology for low power and provides a blueprint for successful verification of low power designs. It describes the common causes of low power design failures, the impact of low power on the specification of power intent, the implementation of test plans, the setup of testbenches and the metrics of verification using assertions and coverage. The VMM-LP builds on the base classes in industry standard VMM to enable the deployment of a consistent, reusable, and scalable power-aware verification environment across multiple design projects within a company. The source code for the VMM-LP base classes documented in VMM-LP will be available free of charge from vmm-central.org later in 2009. In addition to benefitting from the extensive practical experience of the authors from ARM, Synopsys, and Renesas, the VMM-LP is also peer-reviewed by more than 30 low power design and verification experts from around the world.

If you are currently a Synopsys customer, you may download an electronic (PDF) copy of the Verification Methodology Manual for Low Power (VMM-LP) at no cost. You will be asked for your SolvNet ID and password (if you don't have one already, it's easy to register). For more information about the VMM for Low Power, including author bios, information about the silicon technology demonstrators behind the VMM-LP, errata, and addenda information, as well as how to purchase hard copies of the book, please visit the VMM-LP book website.