Available at no cost via electronic (PDF) download to current Synopsys customers. You will be asked for your SolvNet ID and password (if you don't have one already, it's easy to register).
The "Low Power Methodology Manual" (LPMM) is a comprehensive and practical guide to managing power in system-on-chip designs, critical to designers using 90-nanometer and below technology.
The authors, all low power experts, are led by Michael Keating, Synopsys Fellow and principal author of the widely adopted Reuse Methodology Manual for System-on-Chip Design, and David Flynn, ARM R&D Fellow and original architect behind the ARM® synthesizable CPU family and the AMBA® on-chip interconnect protocol.
Combining extensive commercial experience, deep scientific understanding, silicon technology case studies, and a pragmatic approach, the authors describe design techniques which address both dynamic and static (leakage) power, including methods for power gating and dynamic voltage and frequency scaling. For each topic, the authors describe the design challenge, provide a technology foundation, and then make specific recommendations as well as a caution against design pitfalls. This book is a must-read for anyone designing, or getting ready to design, SOC's for low power applications.
If you are currently a Synopsys customer, you may download an electronic (PDF) copy of the Low Power Methodology Manual (LPMM) at no cost. You will be asked for your SolvNet ID and password (if you don't have one already, it's easy to register).
For more information about the LPMM, including author bios, information about the silicon technology demonstrators behind the LPMM, errata, and addenda information, as well as how to purchase hard copies of the book, please visit the LPMM book website.