First of all, the files 'mobile_ddr.v' and 'ddr_params.v' will have to be obtained from Micron.

Installing the Micron DDR models

1. Place mobile_ddr.v and ddr_params.v in
      ${PROJECTSIM}/pl340_dmc_4311/validation/shared/mem_models/verilog/
2. To ensure that the models have a timing speed grade defined, and a data width, edit:
       ${PROJECTSIM}/pl340_dmc4311/validation/shared/mem_models/ \
       verilog/ddr_parameters.v
   by adding:
      `define sg75  // defines speed grade
      `define x16   // defines 16 bit data

Modifying the platform to use the Micron Models

1. Modify:
      $PROJECTSIM/logical/px310_ref_design/validation/shared/px310_host_tbench/ \
       px310_sdrams.v
   by changing:
      `define DENALI
   to:
      `define MICRON
2. Change all instances of mt46h32m16 to mobile_ddr

For system integration

1. Modify:
      $PROJECTSIM/logical/px310_ref_design/validation/integration/scripts/ \
       px310_int_tb_rtl.vc
   by adding:
      -v ${PROJECTSIM}/pl340_dmc_4311/validation/shared/mem_models/verilog/ \
       mobile_ddr.v
2. Modify:
      $PROJECTSIM/logical/px310_ref_design/validation/integration/ \
       makefile
   by adding:
      cp -f ${PROJECTSIM}/pl340_dmc_4311/validation/shared/mem_models/verilog/ \
       ddr_parameters.v ./

For system verification

1. Modify:
      $PROJECTSIM/logical/px310_ref_design/validation/system/ \
       makefile
   by adding:
      cp -f ${PROJECTSIM}/pl340_dmc_4311/validation/shared/mem_models/verilog/ \
       ddr_parameters.v ./
2. Modify:
      $PROJECTSIM/logical/px310_ref_design/validation/system/scripts/ \
       px310_host_sim_tb_rtl.vc
   by adding:
      -v ${PROJECTSIM}/pl340_dmc_4311/validation/shared/mem_models/verilog/ \
       mobile_ddr.v

After making these changes, you will need to run make buildrtl in $PROJECTSIM/logical/px310_ref_design/system, and in $PROJECTSIM/logical/px310_ref_design/integration

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