The following errors appear in the transcript when running the register tests via the script register.cli.txt:

# *Denali* Error: <px310_host_sim_tb.u_px310_sdrams.uk4x28163pe_gc0_3b>@13246927550 ps :: Clock-enable signal has unknown value
# *Denali* Error: <px310_host_sim_tb.u_px310_sdrams.uk4x28163pe_gc0_3a>@13246927550 ps :: Clock-enable signal has unknown value
# *Denali* Error: <px310_host_sim_tb.u_px310_sdrams.uk4x28163pe_gc0_2b>@13246927550 ps :: Clock-enable signal has unknown value
# *Denali* Error: <px310_host_sim_tb.u_px310_sdrams.uk4x28163pe_gc0_2a>@13246927550 ps :: Clock-enable signal has unknown value
# *Denali* Error: <px310_host_sim_tb.u_px310_sdrams.uk4x28163pe_gc0_1b>@13246927550 ps :: Clock-enable signal has unknown value
# *Denali* Error: <px310_host_sim_tb.u_px310_sdrams.uk4x28163pe_gc0_1a>@13246927550 ps :: Clock-enable signal has unknown value
# *Denali* Error: <px310_host_sim_tb.u_px310_sdrams.uk4x28163pe_gc0_0b>@13246927550 ps :: Clock-enable signal has unknown value
# *Denali* Error: <px310_host_sim_tb.u_px310_sdrams.uk4x28163pe_gc0_0a>@13246927550 ps :: Clock-enable signal has unknown value

The Denali error messages are quite 'normal'. They come about because the PL340 Memory Configuration Register has just had the value 0xAAAA written to it as part of the auto-generated register tests. This has the effect of, amongst other things, setting the Auto Power Down bit and placing the value 0x15 into the Power Down Prd bits. Consequently, after 0x15 memory clock cycles, the SDRAM goes into power down mode and the Clock Enable (CKE) is de-asserted.

Back to FAQs index