This document and its supporting files intend to:

• Explain how to use the Versatile/PB926EJ-S as a benchmarking platform
• Provide example code that uses the AHB Monitor performance counters
• Show the timing of accesses to commonly used areas of the memory map
• Calculate the maximum bandwidth on the development chip internal buses and on the external AHB buses

The information provided relates to the AHB masters inside the development chip, especially the ARM926EJ-S and the CLCD controller, and also external AHB masters connected to the AHB S bus.

The newVersatile/AB926EJ-S is based on the same development chip as the Platform Baseboard. Therefore all the information provided about the speed of the ARM926EJ-S processor and the peripherals inside the development chip also applies to this board.