For general information about the JTAG synchronisation logic and debugging with adaptive clocking, please see the FAQ entries: When debugging hard macrocells, the maximum TCK frequency is not directly proportional to the core clock frequency. However, when working at very low speeds, the TCK frequency may need to be reduced to avoid timeouts in the debugger. When the hard macrocell has a variable clock it may be helpful to set the JTAG emulator with adaptive clocking. If this is the case you need to add a JTAG synchronisation block that generates RTCK by passing TCK through three flip-flops clocked with the core clock. Note that the JTAG synchronisation logic is not needed by the hard macrocell itself, unlike synthesizable cores, but is needed by the JTAG emulator to generate a TCK with variable frequency. The JTAG signals TDI, TCK, TMS and TDO should still be connected directly between the hard macrocell and the JTAG connector.
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