[new 19 October 2007]

Many customers want to change clock frequencies in order to make software run faster, benchmark software by scaling down the CPU frequency, or to build a custom motherboard for a Core Tile. The ARM926EJ-S Core Tile example design we provide in application note AN148 gives fairly coarse control over clock frequency. This FAQ describes the test chip signals in more detail than is covered in the Core Tile user guide.

To change the clocks you need to understand the clock circuit described in chapter 4 of the ARM926EJ-S Core Tile user guide.

Maximum CPU frequency for the test chip is given in the printed release notes in the Core Tile box.

Clock control signals

These details are for the ARM926EJ-S test chip marked 'UMC'.

CPU clock is fed from the output of the test chip PLL. So for CPU running at 150MHz given a 25MHz REFCLK, the PLL should multiply by 150/25 = 6. 

The formula for the PLL output frequency is:

CPU frequency = ( ( REFCLK / ( PLLREFDIV + 1 ) ) * ( PLLFBDIV + 1 ) ) / ( PLLOUTDIV + 1 )

PLL reference frequency (output of PLLREFDIV) range is 137kHz - 275MHz
PLL VCO frequency range is 55MHz - 275MHz

The PLL control signals should be set like this:

PLLREFDIV[3:0] = b0000       for divide by 1
PLLFBDIV[7:0]  = b00000101   for divide by 6
PLLOUTDIV[2:0] = b000        for divide by 1
PLLOUTDIV[3]   = b0          not used, recommend tie low
PLLCTRL[1:0]   = b00         to use PLL in normal mode
PLLBYPASS      = b0          to use PLL

To run the external AHB bus clock (HCLKE) at 25MHz you need to divide down the output of the PLL by 150/25 = 6. The clock divider signals should be set like this:

HCLKDIV[2:0]   = b101        for divide by 6
USERIN[1:0]    = b00         most significant bits of HCLKDIV
USERIN[3]      = b0          to disable some undocumented features

Measuring frequency

You can use an oscilloscope to measure the input reference clock (REFCLK) at U18 pin 7, and the output AHB bus clock (HCLK) at U14 pin 41.

You can measure the CPU frequency by timing how long a loop takes to run in zero wait state TCM. See the 'speed test' program in our ARM1136JF-S clocks FAQ, but note taking the branch only takes an ARM9 5 cycles to re-fill the pipeline not 7.

• App Note 148: Using Core Tiles on the Emulation Baseboard
• How do I change the clock frequencies on the ARM1136JF-S Core Tile?
• Core Tile for ARM7TDMI, ARM926EJ-S and ARM1136JF-S User Guide