[new 4 October 2007]

We provide example designs for AHB and AXI peripherals implemented in Logic Tiles, and recommend customers use these as starting points for their own projects. This will help prevent board damage by erroneous pin assignment and facilitates technical support. The example designs include a pin constraints file and RTL for a bus master and slave.

• Application Note 170 RTL shows a Virtex-4 AHB example design for use with a PB926EJ-S baseboard.
• Application Note 146 RTL shows a Virtex-4 AHB example design for use with an Emulation Baseboard.
• Application Note 151 RTL shows a Virtex-4 AXI example design for use with an Emulation Baseboard.

Application notes are provided on the Versatile CD and in the Documentation area of our web site. For a list of which application notes work with which boards, please see this FAQ.