[new 15 August 2007]

The design of the logic tiles enables the user to stack them on top of each other. Logic tiles are based on one of the largest capacity FPGAs. However, a single FPGA is not always large enough for some designs.

Very complex designs can be split into several blocks (partitioning) and each of the blocks can be synthesized in a separate FPGA.

The logic tile provides the infrastructure to interface the different blocks:

• More than 400 signals for connection between each pair of tiles
• Impedance matched, high speed, robust connectors with data rates up to 100MHz
• Selectable interface voltage levels
• Delay matched and re-timed clocks
• JTAG scan-chains for real and virtual TAP controllers