[New 21 February 2007]

Designing an AXI peripheral is difficult. We recommend you use our application note AN151 with an Emulation Baseboard and Logic Tile as a starting point for your design. The CD shipped with our Versatile development boards includes AN151 and the RTL you need for an AXI master and AXI slave.

Please note that we are only able to offer limited support for custom-designed and third-party FPGA boards. Experience has shown that customers attempting this can run into a wide range of difficult problems. If you must design your own board (for example you want a chip or interface that we do not provide on the IT1 Interface Tile) then we recommend you make a small PCB to fit on top of a Logic Tile.

Common problems include:

• You must tie unused handshake control signals inactive. The Emulation Baseboard provides both an AXI master and slave interface on tile site 2. For example, if you are designing an AXI slave you must tie these signals on the master side (HDRX) low: AWVALID, WVALID, BREADY, ARVALID, RREADY.
• The system reset signal nSYSRST may pulse several times during the system initialization, this is due to the configuration of the system FPGA and the PLLs on the CT11MPCore taking 1 to 2 seconds to settle. Any logic tile design should be able to handle these initial SYSRST assertions.