[new 11 January 2007]

The test chips fitted to the CT1156T2F-S have been produced with an incorrect IDCODE for the test chip boundary scan JTAG TAP controller.  The IDCODE of the processor TAP controller has been set correctly, therefore ICE auto detection during a debug session will work as expected.

This IDCODE error will only be noticed when the Core Tile is connected to a system that is in configuration mode, as this is when the ARM's TAP controller is replaced with the boundary scan TAP controller.  Progcards for RVI and USB will auto detect the part as ARM1136J-Sr0_BS2.  As a result of this error, the progcards .brd files have had to be written to match with this incorrect part, functionality of programming FPGA images is not affected. 

If you are using progcards_multiice, then you will need to manually configure the server to show ARM1136J-Sr0_BS2 in order for the .brd files to match & perform programming.

The IDCODE for the processor TAP is 0x07B56F0F (correct)

The IDCODE for the boundary scan TAP is 0x0F21DF0F (incorrect)