[Updated 26 September 2007] The Versatile family CD-ROM supplies schematic diagrams for all of the range of Versatile boards. Traditionally there was a single PDF for each revision of PCB released. This CD (v3.1.1 and later) now has a different file naming convention that has a generic schematic (named <board number and PCB revision>_coredesign.pdf), this is not used for Bill of Materials (BoM) generation - the actual PCB builds (BoMs and schematics) are provided with a letter such as '_a' or '_b' to denote build variants where applicable. Taking the AB926EJ-S as an example, rev C schematics are provided with the new naming convention (shown in bold text): | hpi0118a.pdf | Diagram for the rev A PCB | | hpi0118b.pdf | Diagram for the rev B PCB | | hpi0118c_coredesign.pdf | Generic diagram for the rev C PCB - for all boards, ignore this PDF | | hpi0118c_a.pdf | Build variant 'a' for the rev C PCB | | hpi0118c_b.pdf | Build variant 'b' for the rev C PCB |
Which build variant is my board? The variant letter of a PCB should be marked on the board itself, either handwritten in indelible marker pen, or with a printed sticker. This marking should be in or on a small white rectangle which is part of the silk screen printing, immediately after the PCB part number. The following photograph shows the location on a RevC, build variant A CT1156T2F-S board: 
It has been found that some boards have the build variant letter incorrectly marked on the PCB. In this case, it is not possible to read the build variant letter from the PCB itself and the information below should be used for correct identification. What are the differences between the build variants? The details of the build variants of the Versatile boards are shown below (correct as of December 2006). | AB926EJ-S | | Variant 'a' is the standard build | | Variant 'b' is fitted with taller expansion connectors (J17,J18,J25,J26) - limited release |
| AT1 | | Variant 'a' is the standard build |
| CT7TDMI | | Variant 'a' is fitted with ARM7TDMI r3a (Epson) - check printed info on the test chip | | Variant 'b' is fitted with ARM7TDMI r3a (Hynix) - check printed info on the test chip | | Variant 'c' is fitted with ARM7TDMI r4 (Epson) - check printed info on the test chip |
| CT11MPCore | | Variant 'a' is fitted with a test chip socket - not released | | Variant 'b' is the standard build |
| CT1156 | | Variant 'a' is the standard build | | Variant 'b' is for a future Core Tile - ignore |
| CT_GTC | | Variant 'e' is fitted with a test chip socket - not released | | Variant 'h' is fitted with ARM1136JF-S r0p1 (TSMC) | | Variant 'j' is fitted with ARM926EJ-1616 r0p4 (UMC) |
| EB | | Variant 'a' is the standard build |
| LT_XC4VLXnn0 | | Variant 'a' is fitted with an XC4VLX100 FPGA - not released | | Variant 'b' is fitted with an XC4VLX160 FPGA | | Variant 'c' is fitted with an XC4VLX200 FPGA |
| PB926EJ-S | | Variant 'a' is the standard build | | Variant 'b' is for production test only - not released. |
| PCI Backplane | | Variant 'a' is the standard build | | Variant 'b' is for production test only - not released. |
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