When the Emulation Baseboard (EB) is in debug mode, JTAG access to the programmable devices on the system are available via header J19 (INT LOGIC ANALYSER). This allows tools such as the Xilinx Chipscope to be used with the board, even when a debugger is connected to the ARM core's JTAG signals. This is possible as the EB has two separate JTAG chains, for details please refer to the EB user guide. Our customers have reported that the Chipscope software does not automatically detect some of the devices on the CT11MPCore, these are the two Lattice ispClock5620 devices. They have an IR (TAP controller Instruction Register) size of 8 bits. You may need to add these devices manually to the configuration of the Chipscope tool. Please refer to your Xilinx documentation for this information, as we are unable to provide support for 3rd party tools. As an example, the ordering, naming and IR lengths of a system consisting of an EB + CT11MPCore + Logic Tile 8000 is (with respect to TDI): | TAP | Device Name | Board | IR Length | | 0 | XC2V6000 | EB | 6 | | 1 | ispClock5620 | CT11MPCore | 8 | | 2 | ispClock5620 | CT11MPCore | 8 | | 3 | XC2C384 | CT11MPCore | 8 | | 4 | XC2V8000 | Logic Tile | 6 | | 5 | XC9572XL (may be displayed as XC9500XL) | Logic Tile | 8 |
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