[New 16 Aug 2006]
This FAQ only applies to the revision A PCB, the newer lead free revision B PCB does not have this problem.
As described in various Integrator board user guides, each Integrator board has a set of four signals (nPPRES[3:0] or nEPRES[3:0]) which are used to indicate to a motherboard that extra modules are present in the system. This allows the motherboard to disable the default slave Bus Error (abort) responses for certain address ranges, depending on which expansion modules are fitted.
On many Integrator module boards, the nPPRES(0) signal is connected directly to GND. On the IM-LT3 board, each nPPRES signal is connected to an FPGA I/O and pulled up to 3.3V via 10k. This in theory allows the developer to use the IM-LT3 to control exactly which of the four expansion logic address ranges should cause a default slave response from the motherboard. Unfortunately, the PCB design is slightly incorrect, in that nPPRES(0) and a GND pin are swapped over. These are pins 33 and 34 on HDRB (J7):
As per other Integrator boards, pin 33 should be nPPRES(0) and pin 34 should be GND.
This error has the following implications:
- If the IM-LT3 is stacked on any other Integrator family board, the developer should ensure that the connected FPGA I/Os on the IM-LT3 and any stacked Logic Tiles must NEVER be driven to a logic HIGH. This is because they will be grounded by pin 34 on the adjacent Integrator board(s) and permanent damage to the FPGA I/Os will occur.
- If the IM-LT3 is used on an Integrator motherboard, it is not possible to leave the IM-LT3 address range (which depends on where in the stack the IM-LT3 is placed) under the control of the motherboard. This is because the IM-LT3 will always ground its nPPRES(0) signal. Note that in an Integrator/CP system, the first 256MB expansion logic range (0xC0000000 to 0xCFFFFFFF) is already pre-assigned to system slaves.
In summary, the nPPRES(0) connections on the IM-LT3 and LT are:
Signal (IM-LT3 lower) | Signal (IM-LT3 upper) | IM-LT3 I/O | Signal (LT lower) | Logic Tile I/O |
nPPRES(0) on J7.34 | YU[120] on J1.62 | U6.G7 | YL[120] on J6.62 | U1.AE28 |
For further clarification, please consult the PCB schematics and netlists for all connected boards.
Back to FAQs index
